ST9 datasheet(131/146 Pages) STMICROELECTRONICS

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ST9 USER GUIDE

6 DETAILED BLOCK DIAGRAMS

Here are the detailed block diagrams to supplement to the simplified ones used at various

points throughout this book.

6.7 EXTERNAL INTERRUPT CONTROLLER

Figure 47

. External Interrupt Block Diagram

INT 0 Pin

End of Count WDR

see Timer Watchdog

and reset circuitry

Rising (set) or falling (reset) edge trigger event

Watchdog or INT 0 pin

INT A0 interrupt

to the core

Interrupt pending bit: channel A0

Comparison between

CPL and priority

level of INT A0

0' for INTA0'

These bits are the MSB of the pointers in the

vector table, for the 8 external interrupts.

From another interrupt source;

Hardware interrupt daisy chain

IEN is common

for the 8 external

maskable interrupts

(See the priority level arbitration)

TED1 TED0 TEC1 TEC0 TEB1 TEB0 TEA1 TEA0

EITR (R242 page 0)

External Interrupt Trigger Event Register

IPD1 IPD0 IPC1 IPC0 IPB1 IPB0 IPA1 IPA0

IMD1 IMD0 IMC1

IMB1 IMB0 IMA1 IMA0

Interrupt mask bit channel A0

TEA0: Trigger event of Interrupt Channel A0

IAOS: Interrupt A0 Selection bit

IPA0: Interrupt Pending bit Channel A0 (set and reset by

hardware, except if one wishes a software interrupt)

IMA0: Interrupt Mask Bit Channel A0

CPL(0,1,2):Current priority level of main

PL(1A,2A):Priority level of group INTA0, INTA1

IEN:

Interrupt Enable

level of INT A0

TLTEV TLIS IAOS EWEN

EIVR (R246 page 0)

External Interrupt Vector Register

(See vector table organisation)

EIPR (R243 page 0)

External Interrupt Pending Register

EIMR (R244 page 0)

External Interrupt Mask-bit Register

IMC0

PL2D

PL2C

PL2B PL1B PL2A PL1A

EIPLR (R245 page 0)

External Interrupt Priority Level Register

PL1C

GCEN TLIP TLI

IAM CPL2 CPL1 CPL0

CICR (R230)

Central Interrupt Control Register

IEN

PL1D

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