ST9 datasheet(132/146 Pages) STMICROELECTRONICS

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ST9 USER GUIDE

6.8 TOP-LEVEL INTERRUPT INPUT

Figure 48

. Top-Level Interrupt Block Diagram

NMI pin

Rising (set) or falling

(reset) edge trigger

event on NMI pin

Watchdog or NMI pin

Top level interrupt

A pseudo NMI

Event Interrupt

A real

Event

Top level interrupt to the core

TLI routine has no interrupt vector register.

ISR routine in vector table:

byte4 (high), byte 5 (low) by hardware.

TLTEV:Top level trigger event bit

TLIS:Top level interrupt selection bit

TLIP:Top level interrupt pending bit

(set and reset by hardware only)

TLI:Top level interrupt bit

IEN:Interrupt enable

TLNM:Top level not maskable

Choosing between

End of Count WDR

see Timer Watchdog

and Reset circuitry

V6 V5

TLTEV

TLIS

IAOS EWEN

EIVR (R246 page 0)

External Interrupt Vector Register

GCEN TLIP

TLI

IEN

IAM

CPL2 CPL1 CPL0

CICR (R230)

Central Interrupt Control Register

HL5

HL4 HL3

HL2

HL1

HL0

NICR (R247 page 0)

Nested Interrupt Control Register

TLNM

Nested Interrupt Control Register

HL6

Interrupt

NMI

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