PD62_15 datasheet(28/66 Pages) RENESAS

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µPD62

Data Sheet U14208EJ1V0DS00

6. RESET PIN

The system reset takes effect by inputting low level to the RESET pin.

While the RESET pin is at low level, the system clock oscillator is stopped and the XIN and XOUT pins are fixed

to the GND.

If the RESET pin is raised from low level to high level, it executes the program from the 0 address after counting

246 to 694 of the system clock (fX).

Figure 6-1. Reset Operation by RESET Input

The RESET pin outputs low level when the POC circuit (mask option) is in operation.

Caution When connecting a reset IC to the RESET pin, ensure that the IC is of the N-ch open drain output

type.

Table 6-1. Hardware Statuses After Reset

• RESET Input in Operation

• RESET Input During STANDBY Mode

Hardware

• Resetting by Internal POC Circuit in Operation

• Resetting by the Internal POC Circuit During

• Resetting by Other FactorsNote 1

STANDBY Mode

PC (10 bits)

000H

SP (1 bit)

Data

R0 = DP

000H

memory

R1-RF

Undefined

Previous status retained

Accumulator (A)

Undefined

Status flag (F)

Carry flag (CY)

Timer (10 bits)

000H

Port register

FFH

×FHNote 2

Control register P3

03H

26H

Notes 1. The following resets are available.

• Reset when executing the HALT instruction (when the operand value is illegal or does not satisfy

the precondition)

• Reset when executing the RLZ instruction (when A = 0)

• Reset by stack pointer’s overflow or underflow

2. Refers to the value by the KI pin status.

In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when

reset is released (when RESET pin changes from low level to high level, or POC is released due to

supply voltage startup).

Wait

(246 to 694)/fX +

HALT mode

Oscillation

stopped

OPERATING mode or

STANDBY mode

RESET

0 address start

α : Oscillation growth time

OPERATING

mode

PD62 Datasheet(PDF) 28 Page - Renesas Technology Corp

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