RM0319 datasheet(328/368 Pages) STMICROELECTRONICS

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Power, reset and clock control

RM0319

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Doc ID 022640 Rev 3

30.3

Power management techniques

Power consumption is an important design aspect of any modern system. Power

management techniques allow power consumption to be reduced by ensuring that system

performance is adapted dynamically to the application requirements.

30.3.1

Dynamic Frequency Scaling (applicable in NORMAL state)

This technique uses dynamic selection of the optimal frequency to allow a task to be

performed in the required amount of time.

As described in Section 30.5: Clock control, PLL1 (Sys) provides frequency to the system.

By default, DRAM is driven by PLL1, this mode is called synchronous DRAM. It is also

possible to use PLL2 to drive DRAM, this mode is called asynchronous DRAM.

In asynchronous DRAM mode, you can change the system frequency (PLL1) without

affecting DRAM operations. For this reason, to apply the Dynamic Frequency Scaling

System, the asynchronous DRAM mode must be used.

Frequency changes are applied with a small delay, due to the PLL lock time.

Changing the PLL frequency in NORMAL state generates undesirable frequency

overshoot/undershoot. To avoid this, it is better to switch to Slow state, change PLL

frequency, disable Dithering (if enabled), wait for the PLLlock signal, switch again to Normal

mode and enable Dithering again (if it was originally enabled).

There are two ways to wait PLL stabilization, by software and by hardware, see

Section 30.1.3: SLOW for details.

30.3.2

Dynamic clock switching

Like DFS, Dynamic Clock Switching (DCS) is a power-management technique aimed at

reducing active power consumption of a device, whereas DFS change frequency of all

modules using CLK_Pll1 signal. DCS could switch OFF completely the clock of an unused

modules and quickly switch ON when its use is required.

With this technique the processor, or system, could run at maximum frequency maintained

highest performances.

To have maximum flexibility DCS is fully software controlled through PERIP1_CLK_ENB

DCS is useful when a real-time application is waiting for an event. The system can switch

OFF clock of modules not used and enable them, with a low latency, when needed.

Modules that support this feature are shown in Table 118

Table 118.

Modules supporting DCS technique

Module

GPIO

SPI

SDRAM

RTC

UART

USB 2.0 host

ADC

ARM subsystem

USB 2.0 device

Timer 2

ARM

Ethernet

Timer 3

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