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UPD72042 Datasheet(PDF) 2 Page - NEC |
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UPD72042 Datasheet(HTML) 2 Page - NEC |
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2 / 92 page ![]() µPD72042 2 Data Sheet S14870EJ1V0DS00 PIN CONFIGURATION (TOP VIEW) • 16-pin plastic SOP (9.53 mm (375)) µPD72042GT Note Parentheses indicate the state corresponding to two-wire serial I/O mode. AVDD : Main power supply for IEBus (connected to the VDD pin) BUS–, BUS+ : IEBus I/O C/D : Command/data switch input CS : Chip select input GND : Ground IRQ : Interrupt request output NC : No connection RESET : Reset input SCK : Serial clock input SEL : Serial mode selection SI : Serial data input SIO : Serial data I/O SO : Serial data output TEST : Test input (connected to the VDD pin) VDD : Main power supply XI, XO : System clock 1 2 3 4 5 6 7 8 VDD TEST RESET CS SEL AVDD BUS + BUS − 16 15 14 13 12 11 10 9 SCK SI(SIO) Note SO(NC) Note IRQ C/D XI XO GND |
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