UPD72042 datasheet(23/92 Pages) NEC

23 / 92 page

µPD72042

Data Sheet S14870EJ1V0DS00

Table 3-1

I/O States of the SIO (SI) and SO Pins

RESET

SEL

C/D

SI (SIO)

State

Three-wire/two-wire

Operating mode

××

Hi-Z

–

Reset state

××

Hi-Z

–

Chip nonselected state

Three-wire

Control mode

Data write mode

Data read mode

Hi-Z

Two-wire

Control mode

Data write mode

Data read mode

: Input state

Hi-Z : High-impedance state

: Output state

: Don’t care

O* : State in which 1 is output

3.2

DATA TRANSFER FORMAT

3.2.1

Three-Wire Data Transfer (SEL = 1)

(1) Control mode

When the C/D input is set high, control mode is set to control data transfer. Data transfer control involves the

following processing.

Remark After reset (RESET) cancellation, the state enabling writing to the register at address 0000B is set.

Caution In control mode, each data item is read every eighth clock pulse. (Data of less than eight clock

periods is ignored.)

C/D

SCK

SIO

××

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