LTC3409 datasheet(13/16 Pages) LINER

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LTC3409

3409fc

Notethatathighersupplyvoltages,thejunctiontemperature

is lower due to reduced switch resistance (RDS(ON)).

Checking Transient Response

The regulator loop response can be checked by looking

at the load transient response. Switching regulators take

several cycles to respond to a step in load current. When

a load step occurs, VOUT immediately shifts by an amount

equal to (ΔILOAD • ESR), where ESR is the effective series

resistance of COUT. ΔILOAD also begins to charge or dis-

charge COUT, which generates a feedback error signal. The

regulator loop then acts to return VOUT to its steady state

value. During this recovery time VOUT can be monitored

for overshoot or ringing that would indicate a stability

problem. For a detailed explanation of switching control

loop theory, see Application Note 76.

A second, more severe transient is caused by switching

in loads with large (>1μF) supply bypass capacitors. The

discharged bypass capacitors are effectively put in paral-

lel with COUT, causing a rapid drop in VOUT. No regulator

can deliver enough current to prevent this problem if the

load switch resistance is low and it is driven quickly. The

only solution is to limit the rise time of the switch drive

so that the load rise time is limited to approximately

(25 • CLOAD). Thus, a 10μF capacitor charging to 3.3V

would require a 250μs rise time, limiting the charging

current to about 130mA.

Board Layout Considerations

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the LTC3409. These items are also illustrated graphically

in the layout diagram of Figure 3. Check the following in

your layout.

1. Does the capacitor CIN connect to the power VIN

(Pins 3, 4) and GND (Exposed Pad) as close as pos-

sible? This capacitor provides the AC current to the

internal power MOSFETs and their drivers.

2. Are the COUT and L1 closely connected? The (–) plate of

COUT returns current to GND and the (–) plate of CIN.

3. The resistor divider, R1 and R2, must be connected

between the (+) plate of COUT and a ground sense line

terminated near GND (Exposed Pad). The feedback

signals VFB should be routed away from noisy compo-

nents and traces, such as the SW line (Pins 6), and its

trace should be minimized.

4. Keep sensitive components away from the SW pins.

The input capacitor CIN and the resistors R1 and R2

should be routed away from the SW traces and the

inductors.

5. A ground plane is preferred, but if not available, keep

the signal and power grounds segregated with small

signal components returning to the GND pin at one

point. They should not share the high current path of

CIN or COUT.

6. Flood all unused areas on all layers with copper. Flooding

with copper will reduce the temperature rise of power

components. These copper areas should be connected

to VIN or GND.

VIN

LTC3409

RUN

VFB

SYNC

MODE

CIN

VIN

SGND GND

COUT

3409 F03

VOUT

Figure 3

APPLICATIONS INFORMATION

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