PALCE16V8 datasheet(4/32 Pages) LATTICE

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PALCE16V8 and PALCE16V8Z Families

Registered Output Conﬁguration

The control bit settings are SG0 = 0, SG1 = 1 and SL0x = 0. There is only one registered

conﬁguration. All eight product terms are available as inputs to the OR gate. Data polarity is

determined by SL1x. The ﬂip-ﬂop is loaded on the LOW-to-HIGH transition of CLK. The feedback

path is from Q on the register. The output buffer is enabled by OE.

Combinatorial Conﬁgurations

The PALCE16V8 has three combinatorial output conﬁgurations: dedicated output in a non-

registered device, I/O in a non-registered device and I/O in a registered device.

Dedicated Output in a Non-Registered Device

The control bit settings are SG0 = 1, SG1 = 0 and SL0x = 0. All eight product terms are available

to the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the

exception of pins 15 and 16. Pins 15 and 16 do not use feedback in this mode. Because CLK

and OE are not used in a non-registered device, pins 1 and 11 are available as input signals. Pin

1 will use the feedback path of MC7, and pin 11 will use the feedback path of MC0.

Combinatorial I/O in a Non-Registered Device

The control bit settings are SG0 = 1, SG1 = 1, and SL0x = 1. Only seven product terms are

available to the OR gate. The eighth product term is used to enable the output buffer. The signal

at the I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to

be used as an input.

Because CLK and OE are not used in a non-registered device, pins 1 and 11 are available as

inputs. Pin 1 will use the feedback path of MC7, and pin 11 will use the feedback path of MC0.

Combinatorial I/O in a Registered Device

The control bit settings are SG0 = 0, SG1 = 1 and SL0x = 1. Only seven product terms are available

to the OR gate. The eighth product term is used as the output enable. The feedback signal is the

corresponding I/O signal.

Dedicated Input Conﬁguration

The control bit settings are SG0 = 1, SG1 = 0 and SL0x = 1. The output buffer is disabled. Except

for MC0 and MC7, the feedback signal is an adjacent I/O. For MC0 and MC7, the feedback signals

are pins 1 and 11. These conﬁgurations are summarized in Table 1 and illustrated in Figure 2.

Table 1. Macrocell Conﬁguration

SG0

SG1

SL0X

Cell

Conﬁguration

Devices

Emulated

SG0

SG1

SL0X

Cell

Conﬁguration

Devices

Emulated

Device Uses Registers

Device Uses No Registers

Registered Output

PAL16R8, 16R6,

16R4

100

Combinatorial

Output

PAL10H8, 12H6,

14H4, 16H2, 10L8,

12L6, 14L4, 16L2

011

Combinatorial

I/O

PAL16R6, 16R4

Input

PAL12H6, 14H4,

16H2, 12L6, 14L4,

16L2

111

Combinatorial

I/O

PAL16L8

PALCE16V8 Datasheet(PDF) 4 Page - Lattice Semiconductor

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