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UPD75316GF Datasheet(PDF) 49 Page - NEC |
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UPD75316GF Datasheet(HTML) 49 Page - NEC |
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49 / 62 page ![]() µPD75312(A), 75316(A) 49 SERIAL TRANSFER OPERATION Two-Line and Three-Line Serial I/O Modes (SCK: internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK Cycle Time tKCY1 VDD = 4.5 to 6.0 V 1600 ns 3800 ns SCK High-, Low-Level tKL1 VDD = 4.5 to 6.0 V tKCY1/2-50 ns Widths tKH1 tKCY1/2-150 ns SI Set-Up Time (vs. SCK ↑) tSIK1 150 ns SI Hold Time (vs. SCK ↑ )tKSI1 400 ns SCK ↓→ SO Output tKSO1 RL = 1 k Ω,VDD = 4.5 to 6.0 V 250 ns Delay Time CL = 100 pF* 1000 ns TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: external clock input) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK Cycle Time tKCY2 VDD = 4.5 to 6.0 V 800 ns 3200 ns SCK High-, Low-Level tKL2 VDD = 4.5 to 6.0 V 400 ns Widths tKH2 1600 ns SI Set-Up Time (vs. SCK ↑) tSIK2 100 ns SI Hold Time (vs. SCK ↑)tKSI2 400 ns SCK ↓→ SO Output tKSO2 RL = 1 k Ω, CL = 100 pF* VDD = 4.5 to 6.0 V 300 ns Delay Time 1000 ns *: RL and CL are load resistance and load capacitance of the SO output line. |
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