LT1578CS8 datasheet(15/28 Pages) LINER

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LT1578/LT1578-2.5

conditions. UVLO helps prevent the regulator from oper-

ating at source voltages where these problems might

occur.

Threshold voltage for lockout is about 2.42V. A 3.5

µA bias

current flows

out of the pin at threshold. This internally

generated current is used to force a default high state on

the shutdown pin if the pin is left open. When low shut-

down current is not an issue, the error due to this current

can be minimized by making RLO 10k or less. If shutdown

current is an issue, RLO can be raised to 100k, but the error

due to initial bias current and changes with temperature

should be considered.

()

−

()

−

()

242

3 5

to 100k 25k suggested

VIN = Minimum input voltage

Keep the connections from the resistors to the shutdown

pin short and make sure that interplane or surface capaci-

tance to the switching nodes are minimized. If high resis-

tor values are used, the shutdown pin should be bypassed

with a 1000pF capacitor to prevent coupling problems

from the switch node. If hysteresis is desired in the

undervoltage lockout point, a resistor RFB can be added to

the output node. Resistor values can be calculated from:

V V

OUT

−+

()+

[]

−

()

()(

)

2 42

242

3 5

∆∆

∆

25k suggested for RLO

VIN = Input voltage at which switching stops as input

voltage descends to trip level

∆V = Hysteresis in input voltage level

Example: output voltage is 5V, switching is to stop if input

voltage drops below 12V and should not restart unless

APPLICATIONS INFORMATION

input rises back to 13.5V.

∆V is therefore 1.5V and

VIN = 12V. Let RLO = 25k.

−+

()+

[]

−

()

()=

25 12 2 42 15 5 1

242

25 3 5

25 10 35

233

111

111 5 1 5

370

.. /

SWITCH NODE CONSIDERATIONS

For maximum efficiency, switch rise and fall times are

made as short as possible. To prevent radiated EMI and

high frequency resonance problems, proper layout of the

components connected to the switch node is essential. B

field (magnetic) radiation is minimized by keeping catch

diode, switch pin, and input bypass capacitor leads as

short as possible. E field radiation is kept low by minimiz-

ing the length and area of all traces connected to the switch

pin and BOOST pin. A ground plane should always be used

under the switcher circuitry to prevent interplane cou-

pling. A suggested layout for the critical components is

shown in Figure 5. Note that the feedback resistors and

compensation components are kept as far as possible

from the switch node. Also note that the high current

ground path of the catch diode and input capacitor are kept

very short and separate from the analog ground line.

The high speed switching current path is shown schemati-

cally in Figure 6. Minimum lead length in this path is

essential to ensure clean switching and low EMI. The path

including the switch, catch diode, and input capacitor is

the only one containing nanosecond rise and fall times. If

you follow this path on the PC layout, you will see that it is

irreducibly short. If you move the diode or input capacitor

away from the LT1578, get your resumé in order. The

other paths contain only some combination of DC and

200kHz triwave, so are much less critical.

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