8

LT1637

Open-Loop Gain

0V

10V

OUTPUT VOLTAGE (5V/DIV)

C

1637 G24

1637 G25

Large-Signal Response

1637 G26

Small-Signal Response

A

B

–10V

Supply Voltage

The positive supply pin of the LT1637 should be bypassed

with a small capacitor (about 0.01

µF) within an inch of the

pin. When driving heavy loads an additional 4.7

µF electro-

lytic capacitor should be used. When using split supplies,

the same is true for the negative supply pin.

The LT1637 is protected against reverse battery voltages

up to 25V. In the event a reverse battery condition occurs,

the supply current is typically less than 1nA.

When operating the LT1637 on total supplies of 30V or

more, the supply must not be brought up faster than 1

µs.

This is especially true if low ESR bypass capacitors are

used. A series RLC circuit is formed from the supply lead

inductance and the bypass capacitor. 5

Ω of resistance in

the supply or the bypass capacitor will dampen the tuned

circuit enough to limit the rise time.

TYPICAL PERFOR A CE CHARACTERISTICS

Total Harmonic Distortion + Noise

vs Load Resistance

Total Harmonic Distortion + Noise

vs Output Voltage

LOAD RESISTANCE TO GROUND (

Ω)

0.001

0.01

0.1

1

1k

10k

100k

1637 G22

0.0001

100

0.01

1

10

02

3

1637 G23

0.001

1

0.1

f = 1kHz

A

B

C

10V

– 10V

50mV

– 50mV

APPLICATIO S I FOR ATIO

Inputs

The LT1637 has two input stages, NPN and PNP (see the

Simplified Schematic), resulting in three distinct operat-

ing regions as shown in the Input Bias Current vs Common

Mode typical performance curve.

input stage is active and the input bias current is typically

– 20nA. When the input voltage is about 0.5V or less from

current is typically 80nA. Increases in temperature will

cause the voltage at which operation switches from the

offset voltage of the NPN stage is untrimmed and is

typically 600

µV.