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LT1777

OPERATIO

The LT1777 is a current mode step-down switcher regu-

lator IC designed for low noise operation. The Block

Diagram shows an overall view of the system. The indi-

vidual blocks are straightforward and similar to those

found in traditional designs, including: Internal Bias Regu-

lator, Oscillator, Logic, and Feedback Amplifier. The novel

portion includes a specialized Output Switch section in-

cluding circuits to limit the dI/dt and dV/dt switching rates.

The LT1777 operates much the same as traditional current

mode switchers, the major difference being its specialized

output switch section. Due to space constraints, this

discussion will not reiterate the basics of current mode

switcher/controllers and the “buck” topology. A good

source of information on these topics is Application Note

AN19.

A straightforward output stage is provided by current

source I1 driving the base of PNP transistor Q2. The

collector of Q2 in turn drives the base of NPN output device

Q1. The considerable base/collector capacitance of PNP

Q2 acts to limit dV/dt rate during switch turn-on. However,

when the switch is to be turned off, the only natural limit

to voltage slew rate would be the collector/base capaci-

tance of Q1 providing drive for the same device. While

dependent upon output load level and Q1’s

β, the turn-off

voltage slew rate would be typically much faster than the

turn-on rate. To limit the voltage slew rate on switch turn-

off, an extra function is supplied. This is denoted by the

block labeled “– dV/dt Limiter.”

The details of the – dV/dt Limiter can be seen in the Output

Stage Simplified Schematic. Transistors Q3 and Q4 are

connected in a Darlington configuration whose input is

coupled with small-valued capacitor C1 to the VIN supply

rail. The product of negative voltage slew rate times this

capacitor value equals current, and when this current

through emitter/base resistor R1 exceeds a diode drop, Q3

and then Q4 turn on supplying base drive to output device

Q1 to limit – dV/dt rate.

In addition to voltage rates, the current slew rate also

needs to be controlled for reduced noise behavior. This is

provided by the section in the Block Diagram labeled

“

±dI/dt Limiter.” The details of this circuit can be seen in

the Output Stage Simplified Schematic. Note that an extra,

small-valued inductor, termed the “sense inductor” has

been added to the classic buck topology. As this inductor

is external to the LT1777, its value can be chosen by the

user allowing for optimization on a per application basis.

Operation of the current slew limiter is as follows: The

product of the sense inductor times the dI/dt through it

generates a voltage according to the well known formula

V = (L)(dI/dt). The remainder of the circuit is configured

such that when the voltage across the sense inductor

reaches

±2VBE, drive current will be supplied or removed

as necessary to limit current slew rate. The actual sensing

is performed between the output node labeled VSW and a

new node labeled VD.

In the case of switch turn-on, current drive is provided by

PNP Q2. If the voltage at VSW reaches 2VBE above that at

VD, transistor Q5 turns on and removes a portion of Q2’s

drive from Q1’s base. Similarly for turn-off, as the VSW

node goes 2VBE below VD, transistor Q6 then turns on to

drive Q1’s base as needed. The net effect is that of limiting

the switch node dI/dt in both directions at a rate inversely

proportional to the external sense inductor value.

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