UPD754264 datasheet(8/68 Pages) NEC

8 / 68 page

µPD754264

3.2 Non-port Pins

Pin Name

Input/Output

Alternate

Function

After Reset

I/O Circuit

Function

TYPE Note 1

PTO0

Output

P30

Timer counter output pins

Input

E-B

PTO1

P31

PTO2

P32

INT0

Input

P61

Edge detection vectored

Noise elimination

Input

F -A

interrupt input pin

circuit can be

(detected edge can be

selected.

selected)

Asynchronous

Noise elimination circuit

input

can be selected.

KR4 to KR7

Input

P70 to P73

Falling edge detection testable input pins

Input

B -A

AN0

Input

P62

Analog signal input

Input

F -A

AN1

P63

KRREN

Input

–

Key return reset enable pin

Input

The reset signal is generated at the falling edge

of KRn while KRREN is high in STOP mode.

AVREF

Input

P60

A/D converter reference voltage

Input

F -A

Input

–

Crystal/ceramic resonator (for system clock

–

oscillation) connection pin

When inputting the external clock, input the

–

external clock to pin X1 and input the inverted

phase of the external clock to pin X2.

RESET

Input

–

System reset input pin (low-level active)

–

B -A

Pull-up resistor can be incorporated (mask option).

–

Internally Connected

Connect directly to VDD.–

–

VDD

–

Positive supply pin

–

VSS

–

Ground potential

–

Note

Circled characters indicate the Schmitt-trigger input.

UPD754264 Datasheet(PDF) 8 Page - NEC

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