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LTC1159CS Datasheet(PDF) 14 Page - Linear Technology

Part # LTC1159CS
Description  High Efficiency Synchronous Step-Down Switching Regulators
PDF  20 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC1159CS Datasheet(HTML) 14 Page - Linear Technology

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LTC1159/LTC1159-3.3/LTC1159-5
APPLICATIO S I FOR ATIO
Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1159. These items are also illustrated graphically in
the layout diagram of Figure 8. Check the following in your
layout:
1) Are the signal and power grounds segregated? The
LTC1159 signal ground must connect separately to the
(–) plate of COUT. The other ground pin(s) should return
to the source of the N-channel MOSFET, anode of the
Schottky diode, and (–) plate of CIN, which should have
as short lead lengths as possible.
2) Does the LTC1159 Sense– pin connect to a point close
to RSENSE and the (+) plate of COUT? In adjustable
applications, the resistive divider R1, R2 must be con-
nected between the (+) plate of COUT and signal ground.
3) Are the Sense – and Sense + leads routed together with
minimum PC trace spacing? The differential decoupling
capacitor between the two Sense pins should be as
close as possible to the LTC1159. Up to 100
Ω may be
placed in series with each sense lead to help decouple
the Sense pins. However, when these resistors are
used, the capacitor should be no larger than 1000pF.
4) Does the (+) plate of CIN connect to the source of the
P-channel MOSFET as closely as possible? An addi-
tional 0.1
µF ceramic capacitor between VIN and power
ground may be required in some applications.
5) Is the VCC decoupling capacitor connected closely be-
tween the VCC pins of the LTC1159 and power ground?
This capacitor carries the MOSFET driver peak currents.
6) In adjustable versions, the feedback pin is very sensitive
to pickup from the switch node. Care must be taken to
isolate VFB from possible capacitive coupling of the
inductor switch signal.
7) Is the SHDN1 pin actively pulled to ground during
normal operation? SHDN1 is a high impedance pin and
must not be allowed to float.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
P-GATE
VIN
VCC
P-DRIVE
VCC
CT
ITH
SENSE–
CAP
SHDN2
EXTVCC
N-GATE
P-GND
S-GND
SENSE+
COUT
D1
P-CHANNEL
1k
3300pF
CT
R1
R2
RSENSE
N-CHANNEL
CIN
L
+
–
–
+
VOUT
VIN
OUTPUT DIVIDER
REQUIRED WITH
ADJUSTABLE
VERSION ONLY
BOLD LINES INDICATE HIGH CURRENT PATHS
LTC1159 • F08
1000pF
100pF
+
1
µF
0.15
µF
1N4148
SHUTDOWN
5V EXTVCC
CONNECTION
0.1
µF
VFB
(SHDN1)
Figure 8. LTC1159 Layout Diagram (N and S Packages)



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