LTC1288CS8 datasheet(12/24 Pages) LINER

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LTC1285/LTC1288

Start Bit

The first “logical one” clocked into the DIN input after CS

goes low is the start bit. The start bit initiates the data

transfer. The LTC1288 will ignore all leading zeros which

precede this logical one. After the start bit is received, the

remaining bits of the input word will be clocked in. Further

inputs on the DIN pin are then ignored until the next CS

cycle.

Multiplexer (MUX) Address

The bits of the input word following the START bit assign

the MUX configuration for the requested conversion. For

a given channel selection, the converter will measure the

voltage between the two channels indicated by the “+”

and “–” signs in the selected row of the following tables.

In single-ended mode, all input channels are measured

with respect to GND.

APPLICATION INFORMATION

Data Transfer

The CLK synchronizes the data transfer with each bit

being transmitted on the falling CLK edge and captured

on the rising CLK edge in both transmitting and receiving

systems.

The LTC1285 does not require a configuration input word

and has no DIN pin. A falling CS initiates data transfer as

shown in the LTC1285 operating sequence. After CS falls

the second CLK pulse enables DOUT. After one null bit the

A/D conversion result is output on the DOUT line. Bringing

CS high resets the LTC1285 for the next data exchange.

The LTC1288 first receives input data and then transmits

back the A/D conversion result (half duplex). Because of

the half duplex operation, DIN and DOUT may be tied

together allowing transmission over just 3 wires: CS, CLK

and DATA (DIN/DOUT).

Data transfer is initiated by a falling chip select (CS) signal.

After CS falls the LTC1288 looks for a start bit. After the

start bit is received, the 3-bit input word is shifted into the

DIN input which configures the LTC1288 and starts the

conversion. After one null bit, the result of the conversion

is output on the DOUT line. At the end of the data exchange

CS should be brought high. This resets the LTC1288 in

preparation for the next data exchange.

DIN 1

DIN 2

DOUT 1

DOUT 2

SHIFT MUX

ADDRESS IN

1 NULL BIT

SHIFT A/D CONVERSION

RESULT OUT

LTC1285/88 • AI01

the rising edge of the clock. The input data words are

defined as follows:

ODD/

SIGN

MSBF

START

MUX

ADDRESS

MSB FIRST/

LSB FIRST

LTC1285/88 • AI02

SGL/

DIFF

LTC1288 Channel Selection

MUX ADDRESS

ODD/SIGN

CHANNEL #

–

GND

–

SINGLE-ENDED

MUX MODE

DIFFERENTIAL

MUX MODE

LTC1285/88 • AI03

SGL/DIFF

MSB First/LSB First (MSBF)

The output data of the LTC1288 is programmed for

MSB first or LSB first sequence using the MSBF bit.

When the MSBF bit is a logical one, data will appear on

the DOUT line in MSB first format. Logical zeros will be

filled in indefinitely following the last data bit. When the

MSBF bit is a logical zero, LSB first data will follow the

normal MSB first data on the DOUT line (see Operating

Sequence).

Input Data Word

The LTC1285 requires no DIN word. It is permanently

configured to have a single differential input. The conver-

sion result appears on the DOUT line. The data format is

MSB first followed by the LSB sequence. This provides

easy interface to MSB or LSB first serial ports. For MSB

first data the CS signal can be taken high after B0 (see

Figure 1). The LTC1288 clocks data into the DIN input on

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