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LTC1343 Datasheet(PDF) 5 Page - Linear Technology |
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LTC1343 Datasheet(HTML) 5 Page - Linear Technology |
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5 / 28 page  5 LTC1343 VDD (Pin 1): Generated Positive Supply Voltage for RS232. Connect a 1 µF capacitor to ground. C1+ (Pin 2): Capacitor C1 Positive Terminal. Connect a 1 µF capacitor between C1+ and C1–. PWRVCC (Pin 3): Positive Supply for the Charge Pump. 4.75V ≤ PWRVCC ≤ 5.25V. Tie to VCC (Pin 8) and bypass with a 1 µF capacitor to ground. PIN FUNCTIONS C1– (Pin 4): Capacitor C1 Negative Terminal. D1 (Pin 5): TTL Level Driver 1 Input. D2 (Pin 6): TTL Level Driver 2 Input. D3 (Pin 7): TTL Level Driver 3 Input. Becomes a CMOS level output when the chip is in the echoed clock mode (EC = 0V). Note 1: Absolute Maximum Ratings are those beyond which the safety of a device may be impaired. Note 2: All currents into device pins are positive; all currents out of device are negative. All voltages are referenced to device ground unless otherwise specified. Note 3: All typicals are given for VCC = 5V, C1 = C2 = CVCC = CVDD = 1µF, CVEE = 3.3µF tantalum capacitors and TA = 25°C. ELECTRICAL CHARACTERISTICS The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V (Notes 2, 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V.10 Receiver VTH Receiver Input Threshold Voltage 0 °C ≤ TA ≤ 70°C q – 0.2 0.2 V –7V ≤ VCM ≤ 7V, –40°C ≤ TA ≤ 85°C q – 0.3 0.3 V ∆VTH Receiver Input Hysteresis q 11 50 mV IIN Receiver Input Current – 10V ≤ VA ≤ 10V q ±0.50 mA RIN Receiver Input Impedance – 10V ≤ VA ≤ 10V q 20 30 k Ω tr, tf Rise or Fall Time (Figures 5, 9) 15 ns tPLH Input to Output (Figures 5, 9) 350 ns tPHL Input to Output (Figures 5, 9) 350 ns V.28 Driver VO Output Voltage Open Circuit ±10 V RL = 3k (Figure 4) q ±5 7.6 V ISS Short-Circuit Current VO = GND q ±150 mA IOZ Output Leakage Current – 0.25V ≤ VO ≤ 0.25V, Power Off or q ±0.01 ±100 µA No-Cable Mode or Driver Disabled SR Slew Rate (Figures 4, 8), RL = 3k, CL = 2500pF q 4.0 30.0 V/ µs tPLH Input to Output (Figures 4, 8), RL = 3k, CL = 2500pF q 1.6 2.5 µs tPHL Input to Output (Figures 4, 8), RL = 3k, CL = 2500pF q 1.6 2.5 µs V.28 Receiver VTHL Input Low Threshold Voltage q 1.4 0.8 V VTLH Input High Threshold Voltage q 2.0 1.4 V ∆VTH Receiver Input Hysteresis q 0.1 0.4 1.0 V RIN Receiver Input Impedance – 15V ≤ VA ≤ 15V q 357 k Ω tr, tf Rise or Fall Time (Figures 5, 9) 15 ns tPLH Input to Output (Figures 5, 9), CTRL = 0V 110 ns CTRL = VCC q 330 800 ns tPHL Input to Output (Figures 5, 9), CTRL = 0V 170 ns CTRL = VCC q 480 800 ns |
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