1

LTC1416

Low Power 14-Bit, 400ksps

Sampling ADC

APPLICATI

TYPICAL

Complete, 70mW, 14-Bit ADC with 80.5dB S/(N + D)

BUSY

CS

CONVST

RD

SHDN

14-BIT ADC

14

S/H

BUFFER

4k

LTC1416

•

•

•

D13 (MSB)

D0 (LSB)

–5V

+

–

REFCOMP

1

µF

22

µF

10

µF

10

µF

AGND

1416 TA01

DGND

2.5V

REFERENCE

TIMING

AND

LOGIC

OUTPUT

BUFFERS

INPUT FREQUENCY (Hz)

1k

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

86

80

74

68

62

10k

100k

1416 TA02

1M 2M

NYQUIST

FREQUENCY

Effective Bits and

Signal-to-(Noise + Distortion)

vs Input Frequency

S

FEATURE

s

Sample Rate: 400ksps

s

Power Dissipation: 70mW

s

Guaranteed

s

80.5dB S/(N + D) and 93dB THD at 100kHz

s

80dB S/(N + D) and 90dB THD at Nyquist

s

Nap and Sleep Shutdown Modes

s

Operates with Internal or External Reference

s

True Differential Inputs Reject Common Mode Noise

s

15MHz Full Power Bandwidth Sampling

s

±2.5V Bipolar Input Range

s

28-Pin SSOP Package

S

APPLICATI

, LTC and LT are registered trademarks of Linear Technology Corporation.

s

Telecommunications

s

Digital Signal Processing

s

Multiplexed Data Acquisition Systems

s

High Speed Data Acquisition

s

Spectrum Analysis

s

Imaging Systems

The LTC

µs, 400ksps, 14-bit sampling A/D

converter that draws only 70mW from

±5V supplies. This

easy-to-use device includes a high dynamic range sample-

and-hold and a precision reference. Two digitally select-

able power shutdown modes provide flexibility for low

power systems.

The LTC1416’s full-scale input range is

±2.5V. Maximum

DC specifications include

±2LSB INL, ±1.5LSB DNL over

temperature. Outstanding AC performance includes 80.5dB

S/(N + D) and 93dB THD with a 100kHz input, and 80dB

S/(N + D) and 90dB THD at the Nyquist input frequency of

200kHz.

The unique differential input sample-and-hold can ac-

quire single-ended or differential input signals up to its

15MHz bandwidth. The 60dB common mode rejection

allows users to eliminate ground loops and common

mode noise by measuring signals differentially from the

source.

The ADC has a

µP compatible, 14-bit parallel output port.

There is no pipeline delay in the conversion results. A

separate convert start input and a data ready signal

(BUSY) ease connections to FIFOs, DSPs and micropro-

cessors.

DESCRIPTIO