LTC1530CS8 datasheet(16/24 Pages) LINER

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LTC1530

Thermal Considerations

Limit the LTC1530’s junction temperature to less than

125

°C. The LTC1530’s SO-8 package is rated at 130°C/W

and care must be taken to ensure that the worst-case input

voltage and gate drive load current requirements do not

cause excessive die temperatures. Short-circuit or fault

conditions may activate the internal thermal shutdown

circuit.

LAYOUT CONSIDERATIONS

When laying out the printed circuit board (PCB), the

following checklist should be used to ensure proper

operation of the LTC1530. These items are illustrated

graphically in the layout diagram of Figure 9. The thicker

lines show the high current power paths. Note that at 10A

current levels or above, current density in the PCB itself is

a serious concern. Traces carrying high current should be

as wide as possible. For example, a PCB fabricated with

2oz copper requires a minimum trace width of 0.15" to

carry 10A, and only if trace length is kept short.

1. In general, begin the layout with the location of the

power devices. Orient the power circuitry so that a clean

power flow path is achieved. Maximize conductor widths

but minimize conductor lengths. Keep high current

connections on one side of the PCB if possible. If not,

minimize the use of vias and keep the current density in

the vias to <1A/via, preferably < 0.5A/via. After achiev-

ing a satisfactory power path layout, proceed with the

control circuitry layout. It is much easier to find routes

for the relatively small traces in the control circuits than

it is to find circuitous routes for high current paths.

2. Tie the GND pin to the ground plane at a single point,

preferably at a fairly quiet point in the circuit, such as the

bottom of the output capacitors. However, this is not

always practical due to physical constraints. Connect

the low side source to the input capacitor ground.

Connect the input and output capacitor to the ground

plane. Run a separate trace for the low side FET source

to the input capacitors. Do not tie this single point

ground in the trace run between the low side FET source

and the input capacitor ground. This area of the ground

plane is very noisy.

3. Locate the small signal resistor and capacitors used for

frequency compensation close to the COMP pin. Use a

separate ground trace for these components that ties

directly to the GND pin of the LTC1530. Do not connect

these components to the ground plane!

4. Place the PVCC decoupling capacitor as close to the

LTC1530 as possible. The 10

µFbypasscapacitorshown

at PVCC helps provide optimum regulation performance

by minimizing ripple at the PVCC pin.

5. Connect the (+) plate of CIN as close as possible to the

drain of the upper MOSFET. LTC recommends an

additional 1

µF low ESR ceramic capacitor between VIN

and power ground.

6. The VSENSE/VOUT pin is very sensitive to pickup from the

switching node. Care must be taken to isolate this pin

from capacitive coupling to the high current inductor

switching signals. A 0.1

µF is recommended between

the VOUT pin and the GND pin directly at the LTC1530 for

fixed voltage versions. For the adjustable voltage ver-

sion, keep the resistor divider close to the LTC1530.

The bottom resistor’s ground connection should tie

directly to the LTC1530’s GND pin.

7. Kelvin sense IMAX and IFB at the drain and source pins

of Q1.

8. Minimize the length of the gate lead connections.

APPLICATIO S I FOR ATIO

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