LTC1668I datasheet(7/16 Pages) LINER

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LTC1668

APPLICATIO S I FOR ATIO

Substituting the values found earlier for IOUT A, IOUT B and

IOUTFS:

VDIFF = {2 • DAC Code – 65535)/65536} • 8 •

(RLOAD/RSET) • (VREF)

(7)

From these equations some of the advantages of differen-

tial mode operation can be seen. First, any common mode

noise or error on IOUTA and IOUTB is cancelled. Second, the

signal power is twice as large as in the single-ended case.

Third, any errors and noise that multiply times IOUT A and

IOUT B, such as reference or IOUTFS noise, cancel near

midscale, where AC signal waveforms tend to spend the

most time. Fourth, this transfer function is bipolar; e.g. the

output swings positive and negative around a zero output

at mid-scale input, which is more convenient for AC

applications.

Note that the term (RLOAD/RSET) appears in both the

differential and single-ended transfer functions. This means

that the Gain Error of the DAC depends on the ratio of

RLOAD to RSET, and the Gain Error tempco is affected by the

temperature tracking of RLOAD with RSET. Note also that

the absolute tempco of RLOAD is very critical for DC

nonlinearity. As the DAC output changes from 0mA to

10mA the RLOAD resistor will heat up slightly, and even a

very low tempco can produce enough INL bowing to be

significant at the 16-bit level. This effect disappears with

medium to high frequency AC signals due to the slow

thermal time constant of the load resistor.

Analog Outputs

The LTC1668 has two complementary current outputs,

IOUT A and IOUT B (see DAC Transfer Function). The output

impedance of IOUT A and IOUT B (RIOUT A and RIOUT B) is

typically 1.1k

Ω to LADCOM. (See the Equivalent Analog

Output Circuit, Figure 1.) The LADCOM pin is the com-

mon connection for the internal DAC attenuator ladder. It

usually is tied to analog ground, but more generally it

should connect to the same potential as the lead resistors

on IOUT A and IOUT B. The LADCOM pin carries a constant

current to VSS of approximately 0.32 • (IOUTFS), plus any

current that flows from IOUT A and IOUT B through the

RIOUT A and RIOUT B resistors.

The specified output compliance voltage range is

±1V.The

DC linearity specifications, INL and DNL, are trimmed and

guaranteed on IOUT A into the virtual ground of an

I-to-V converter, but are typically very good over the full

output compliance range. Above 1V the output current will

start to increase as the DAC current steering switch

impedance decreases, degrading both DC and AC linear-

ity. Below – 1V, the DAC switches will start to approach the

transition from saturation to linear region. This will de-

grade AC performance first, due to nonlinear capacitance

and increased glitch impulse. AC distortion performance

is optimal at amplitudes less than

±0.5VP-P on IOUT A and

IOUT B due to nonlinear capacitance and other large-signal

effects. At first glance, it may seem counter-intuitive to

decrease the signal amplitude when trying to optimize

SFDR. However, the error sources that affect AC perfor-

mance generally behave as additive currents, so decreas-

ing the load impedance to reduce signal voltage amplitude

will reduce most spurious signals by the same amount.

The LTC1668 is specified to operate with full-scale output

current, IOUTFS, from the nominal 10mA down to 1mA.

This can be useful to reduce power dissipation or to adjust

full-scale value. However, that the LTC1668 DC and AC

accuracy is specified only at IOUTFS = 10mA, and DC and

AC accuracy will fall off significantly at lower IOUTFS values.

At IOUTFS = 1mA, INL and DNL typically degrade to the 14-

bit to 13-bit level, compared to 16-bit to 15-bit typical

accuracy at 10mA IOUTFS. Increasing IOUTFS from 1mA, the

RIOUT B

1.1k

5pF

LTC1668

5pF

–5V

1668 F01

RIOUT A

1.1k

LADCOM

IOUT A

IOUT B

VSS

52.3

Ω

52.3

Ω

Figure 1. Equivalent Analog Output Circuit

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