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LF2242 Datasheet(PDF) 1 Page - LOGIC Devices Incorporated |
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LF2242 Datasheet(HTML) 1 Page - LOGIC Devices Incorporated |
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1 / 8 page  DEVICES INCORPORATED LF2242 12/16-bit Half-Band Interpolating/ Decimating Digital Filter Video Imaging Products 1 08/16/2000–LDS.2242-K LF2242 12/16-bit Half-Band Interpolating/ Decimating Digital Filter DEVICES INCORPORATED u u u u u 40 MHz Clock Rate u u u u u Passband (0 to 0.22fS) Ripple: ±0.02 dB u u u u u Stopband (0.28fS to 0.5fS) Rejection: 59.4 dB u u u u u User-Selectable 2:1 Decimation or 1:2 Interpolation u u u u u 12-bit Two’s Complement Input and 16-bit Output with User-Selectable Rounding, 8- to 16-Bits u u u u u User-Selectable Two’s Complement or Inverted Offset Binary Output Formats u u u u u Three-State Outputs u u u u u Replaces TRW/ Raytheon/ Fairchild TMC2242 u u u u u Package Styles Available: • 44-pin PLCC, J-Lead • 44-pin PQFP FEATURES DESCRIPTION The LF2242 is a linear-phase, half- band (low pass) interpolating/ decimating digital filter that, unlike intricate analog filters, requires no tuning. The LF2242 can also signifi- cantly reduce the complexity of traditional analog anti-aliasing pre- filters without compromising the signal bandwidth or attenuation. This can be achieved by using the LF2242 as a decimating post-filter with an A/D converter and by sampling the signal at twice the rate needed. Likewise, by using the LF2242 as an interpolating pre-filter with a D/A converter, the corresponding analog reconstruction post-filter circuitry can be simplified. The coefficients of the LF2242 are fixed, and the only user programming required is the selection of the mode (interpolate, decimate, or pass- through) and rounding. The asyn- chronous three-state output enable control simplifies interfacing to a bus. Data can be input into the LF2242 at a rate of up to 40 million samples per second. Within the 40 MHz I/O limit, the output sample rate can be one- half, equal to, or two times the input sample rate. Once data is clocked in, the 55-value output response begins after 7 clock cycles and ends after 61 clock cycles. The pipeline latency from the input of an impulse response to its corresponding output peak is 34 clock cycles. The output data may be in either two’s complement format or inverted offset binary format. To avoid truncation errors, the output data is always internally rounded before it is latched into the output register. Rounding is user-selectable, and the output data can be rounded from 16 bit values down to 8 bit values. DC gain of the LF2242 is 1.0015 (0.0126 dB) in pass-through and decimate modes and 0.5007 (–3.004 dB) in interpolate mode. Passband ripple does not exceed ±0.02 dB from 0 to 0.22fS with stopband attenuation greater than 59.4 dB from 0.28fS to 0.5fS (Nyquist frequency). The response of the filter is –6 dB at 0.25fS. Full compliance with CCIR Recom- mendation 601 (–12 dB at 0.25fS) can be achieved by cascading two devices serially. LF2242 BLOCK DIAGRAM OE TO ALL REGISTERS SI11–0 INTERPOLATION CIRCUIT 55-TAP FIR FILTER ROUND AND LIMIT CIRCUIT DECIMATION CIRCUIT 16 3 3 RND2–0 TCO SO15–0 3 3 SYNC INT DEC CLK 16 12 12 |
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