UPD78C12AL datasheet(8/66 Pages) NEC

8 / 66 page

µPD78C10A,78C11A,78C12A

µPD78C11A and 78C12A sets MODE0 pin to “0” (low level), and MODE1 pin to “1” (high

level*)

µPD78C10A allows you to set MODE0, MODE1 pins to select 4K, 16K, or 64K bytes for the

size of the memory which is installed externally.

MODE0

MODE1

External Memory

4K bytes

16K bytes

64K bytes

Also, when each of MODE0 and MODE1 pins is set to “1”*, it is synchronized to ALE to output

a control signal.

1.1

LIST OF PIN FUNCTION (2/2)

Function

Pin Name

I/O

Input-output

MODE0

MODE1

(Mode)

Input

Control signal input pin in hardware STOP mode. The oscillation stops when a clock is

supplied from outside.

8 pins of analog input to A/D converter. AN7 to AN4 can be used as edge detection (falling

edge) input.

Pull-up. Pull-up resister R is 4 [k

Ω] ≤ R ≤ 0.4 tCYC [kΩ] (tCYC is ns unit).

Remarks The

µPD78C11A and µPD78C12A are pull-up resistor incorporation specifiable by mask option at ports

A, B and C.

NMI

(Non-Maskable

Interrupt)

INT1

(Interrupt

Request)

Input

Non-maskable interrupt input pin of the edge trigger (falling edge)

A maskable interrupt input pin of the edge trigger (rising edge). Also, it can be used as a

zero-cross detection pin for AC input.

Input

AN7 to AN0

(Analog Input)

VAREF

(Reference

Voltage)

Input

A common pin serving both as a standard voltage input pin for A/D converter and as a

control pin for A/D converter operation.

AVDD

(Analog VDD)

Power supply pin for A/D converter.

AVSS

(Analog VSS)

GND pin for A/D converter.

X1, X2

(Crystal)

RESET

(Reset)

STOP

(Stop)

VDD

VSS

Crystal connection pins for system clock oscillation. X1 should be input when a clock is

supplied from outside. Input the clock of the reverse phase of X1 to X2.

Input

Low-level active system reset input.

Positive power supply pin.

GND pin.

UPD78C12AL Datasheet(PDF) 8 Page - NEC

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