4 of 11

RF5355

DS110618

7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.

Pin

Function

Description

Interface Schematic

1VC1

First stage supply voltage.

2RF IN

RF input. Input is matched to 50

 and DC block is provided internally.

3VREG

First, second and third stage bias voltage combined on the die to one exter-

nal voltage. This pin requires regulated supply for best performance.

4PDETECT

Power detector voltage is proportional to RF output power. May need exter-

nal decoupling capacitor for module stability. May need external circuitry to

bring output voltage to desired level.

5RF OUT

RF output is internally matched to 50

 and DC-blocking capacitor of about

1.8pF to 5.6pF depending on the layout is required externally if a switch is

used immediately after the PA that has DC voltage at the switch input

which is the same node at the RF output of the PA.

6RF OUT

Same as pin 5.

See pin 5.

7VC3

Supply voltage for the third stage.

8VC2

Supply voltage for the second stage.

Pkg

Base

GND

Ground connection. The backside of the package should be connected to

the ground plane through a short path (i.e., vias under the device will be

required).

INPUT

MATCH

VC1

INTERSTAGE

MATCH

OUTPUT

MATCH

VC3