+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

16

______________________________________________________________________________________

determines clock mode and power-down states. For

example, if the DIN word contains PD1 = 1, then the

chip remains powered up. If PD0 = PD1 = 0, a

power-down resumes after one conversion.

Hardware Power-Down

Pulling SHDN low places the converter in hardware

power-down (Table 6). Unlike software power-down

mode, the conversion is not completed; it stops coin-

cidentally with SHDN being brought low. SHDN also

controls the clock frequency in internal clock mode.

Letting SHDN float sets the internal clock frequency to

1.8MHz. When returning to normal operation with SHDN

Pulling SHDN high sets internal clock frequency to

225kHz. This feature eases the settling-time requirement

for the reference voltage. With an external reference, the

MAX1246/MAX1247 can be considered fully powered up

within 2µs of actively pulling SHDN high.

POWERED UP

HARDWARE

POWER-

DOWN

POWERED UP

POWERED UP

12 DATA BITS

12 DATA BITS

INVALID

DATA

VALID

DATA

EXTERNAL

EXTERNAL

S X X X X X 1 1

S

0 0

X

X

X

X

X

X X X X X

S

1 1

SOFTWARE

POWER-DOWN

MODE

DOUT

DIN

CLOCK

MODE

SHDN

SETS EXTERNAL

CLOCK MODE

SETS EXTERNAL

CLOCK MODE

SETS SOFTWARE

POWER-DOWN

POWER-DOWN

POWERED UP

POWERED UP

DATA VALID

DATA VALID

INTERNAL

S X X X X X 1 0

S

0 0

X

X

X

X

X

S

MODE

DOUT

DIN

CLOCK

MODE

SETS INTERNAL

CLOCK MODE

SETS

POWER-DOWN

CONVERSION

CONVERSION

SSTRB

Figure 11a. Timing Diagram Power-Down Modes, External Clock

Figure 11b. Timing Diagram Power-Down Modes, Internal Clock