Multirange, +5V, 8-Channel,

Serial 12-Bit ADCs

8

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Pin Description

PIN

PDIP

SSOP

NAME

FUNCTION

11

+5V Supply. Bypass with a 0.1µF capacitor to AGND.

2, 4

2, 3

DGND

Digital Ground

3, 9,

22, 24

4, 7, 8,

11, 22,

24, 25, 28

N.C.

No Connection. No internal connection.

55

SCLK

Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also

sets the conversion speed.

66

CS

Active-Low Chip-Select Input. Data is not clocked into DIN unless CS is low. When CS is high,

DOUT is high impedance.

79

DIN

Serial Data Input. Data is clocked in on the rising edge of SCLK.

810

SSTRB

Serial Strobe Output. In internal clock mode, SSTRB goes low after the falling edge of the eighth

SCLK and returns high when the conversion is done. In external clock mode, SSTRB pulses high

for one clock period before the MSB decision. High impedance when CS is high in external

clock mode.

10

12

DOUT

Serial Data Output. Data is clocked out on the falling edge of SCLK. High impedance when CS is

high.

11

13

SHDN

Shutdown Input. When low, device is in FULLPD mode. Connect high for normal operation.

12

14

AGND

Analog Ground

13–20

15–21, 23

CH0–CH7

Analog Input Channels

21

26

REFADJ

Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a 0.01µF capacitor to AGND.

23

27

REF

Reference-Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer

provides a 4.096V nominal output, externally adjustable to REFADJ. In external reference mode,

0

1

2

3

4

5

6

7

8

0.1

1

10

100

1000

AVERAGE SUPPLY CURRENT vs.

CONVERSION RATE (USING STANDBY)

CONVERSION RATE (ksps)

EXTERNAL CLOCK MODE.

LOW-RANGE UNIPOLAR MODE.

0

1

2

3

4

5

6

7

8

0.1

1

10

100

1000

AVERAGE SUPPLY CURRENT vs.

CONVERSION RATE (USING FULLPD)

CONVERSION RATE (ksps)

EXTERNAL CLOCK MODE.

LOW-RANGE UNIPOLAR MODE.

Typical Operating Characteristics (continued)