Multirange, +5V, 8-Channel,

Serial 12-Bit ADCs

14

______________________________________________________________________________________

conversion in progress. Figure 10 shows the SSTRB

timing in internal clock mode.

Internal clock mode conversions can be completed

with 13 external clocks per conversion but require a

waiting period of 15µs for the conversion to be com-

pleted (Figure 11).

Most microcontrollers require that conversions occur in

multiples of 8 SCLK clock cycles. Sixteen clock cycles

per conversion (as shown in Figure 12) is typically the

most convenient way for a microcontroller to drive the

MAX1270/MAX1271.

Applications Information

Power-On Reset

The MAX1270/MAX1271 power up in normal operation

(all internal circuitry active) and internal clock mode,

waiting for a start bit. The contents of the output data

register are cleared at power-up.

Internal or External Reference

The MAX1270/MAX1271 operate with either an internal

or external reference. An external reference is connect-

ed to either REF or REFADJ (Figure 13). The REFADJ

internal buffer gain is trimmed to 1.638V to provide

4.096V at REF from a 2.5V reference.

SSTRB

CS

SCLK

DIN

DOUT

1

8

20

START SEL2 SEL1 SEL0 RNG

BIP

PD1

PD0

D11 D10

D1

D0

ACQUISITION

FILLED WITH ZEROS

CONVERSION

A/D STATE

910

19

16 INT CLK

12 INT CLK

MSB

LSB

MSB

LSB

2 EXT SCLK

+4 INT CLK

HIGH-Z

HIGH-Z

HIGH-Z

Figure 9. Internal Clock Mode—20 SCLK/Conversion Timing

SCLK #8

NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.

SSTRB

SCLK

CS

Figure 10. Internal Clock Mode—SSTRB Detailed Timing