The offset TC DAC output is fed into the output sum-

ming junction where it is gained by approximately 2.3,

thereby increasing the offset TC correction range. The

buffered FSOTC DAC output is available at FSOTC and

Internal Resistors

with the FSOTC DAC) compensates the FSOTC errors.

Ω. If

disabled by setting the appropriate bit (address 07h

reset to zero) in the configuration register (Table 3).

+4600ppm/°C and a nominal resistance of 100k

Ω at

+25°C. This resistor can be used with certain sensor

types that require an external temperature sensor. The

of the MAX1459.

Internal EEPROM

The MAX1459 has a 128-bit internal EEPROM arranged

as eight 16-bit registers. The 4 uppermost bits for each

register are reserved. The internal EEPROM is used to

store the following (also shown in the memory map in

Table 4):

• Configuration register (Table 3)

• 12-bit calibration coefficients for the offset and FSO

DACs

• 12-bit compensation coefficients for the offset TC

and FSOTC DACs

• Two general-purpose registers available to the user

for storing process information such as serial num-

ber, batch date, and check sums

The EEPROM is bit addressable. Program the EEPROM

using the following steps, where the bits have address-

es from 0 to 127 (07F hex):

1) Read the entire EEPROM, and temporarily store the

reserved bits.

2) Erase the entire EEPROM, which causes all bits to

be 0 (see the ERASE EEPROM Command section).

3) Program 1 to the required bits, including the reserved

bits (see the WRITE EEPROM BIT Command section).

4) Read the whole EEPROM, either with the READ EEP-

ROM BIT or with the READ EEPROM MATRIX com-

mands (see the READ EEPROM BIT Command and

READ EEPROM MATRIX Command sections).

Configuration Register

The configuration register (Table 3) determines the

PGA gain, the polarity of the offset and offset TC coeffi-

cients, and the coarse offset correction (IRO DAC). It

DAC Registers

The offset, offset TC, FSO, and FSOTC registers store

the coefficients used by their respective calibration/

compensation DACs.

Detailed Description of the Digital Lines

Chip-Select (CS) and Write-Enable (WE)

CS is used to enable OUT, control serial communica-

tion, and force an update of the configuration and DAC

registers:

• A low on CS disables serial communication and

places OUT in a high-impedance state.

• A transition from low to high on CS forces an update

of the configuration and DAC registers from the

2-Wire, 4–20mA

Smart Signal Conditioner

_______________________________________________________________________________________

9

Table 3. Configuration Register

Description

01

1

00

03

0

3

02

2

05

5

04

07

4

7

06

6

09

BIT

9

EEPROM

ADDRESS (hex)

08

0B

8

11

0A

10

Offset TC Sign Bit, SOTC

Offset Sign Bit, SOFF

PGA Gain (LSB), A0

PGA Gain, A1

PGA Gain (MSB), A2

Temperature Sensor Selection Bit

Reserved “0”

(0 = enable internal), IRS

IRO LSB, C0

IRO, C1

IRO MSB, C2

DESCRIPTION

CONFIGURATION REGISTER