MAX1459CSLASHD datasheet(5/24 Pages) MAXIM

5 / 24 page

2-Wire, 4–20mA

Smart Signal Conditioner

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Temperature Sensor Terminal 1

TEMP1

Temperature Sensor Terminal 2. RTEMP is a 100k

Ω temperature-dependent resistor with 4600ppm/°C

tempco.

TEMP2

Output Voltage. OUT is a Rail-to-Rail® output that can drive resistive loads down to 10k

Ω and capacitive

loads up to 0.1µF.

OUT

Negative Power Supply

VSS

Sensor Excitation Current Output. The current source that drives the bridge.

BDRIVE

Positive Sensor Input. Input impedance is typically 1M

Ω. Rail-to-rail input range.

INP

Negative Sensor Input. Input impedance is typically 1M

Ω. Rail-to-rail input range.

INM

Auxiliary Op Amp Negative Input

AMP-

Auxiliary Op Amp Output

AMPOUT

Input pin for an External Temperature-Dependent Reference Voltage for FSOTC DAC and OTC DAC. In the

default mode, the MAX1459 uses the temperature-dependent bridge drive voltage as the FSOTC DAC and

OTC DAC reference.

TEMPIN

Current Source Reference. An internal 100k

Ω resistor (RISRC) connects ISRC to VSS (see Functional

Diagram). Optionally, external resistors can be used in place of or in parallel with RFTC and RISRC.

ISRC

Auxiliary Op Amp Positive Input

AMP+

Buffered Full-Span Output Temperature Coefficient DAC Output. An internal 100k

Ω resistor (RFTC) con-

nects FSOTC to ISRC (see Functional Diagram). Optionally, external resistors can be used in place of or in

parallel with RFTC and RISC.

FSOTC

Write Enable, Dual-Function Input Pin. Used to enable EEPROM erase/write operations. Also used to set

the DAC refresh-rate mode. Internally pulled to VDD with a 1M

Ω (typ) resistor. See the Chip-Select (CS)

and Write-Enable (WE) section.

Data Input/Output. Used only during programming/testing. Internally pulled to VSS with a 1M

Ω (typical)

resistor. High impedance when CS is low.

DIO

Positive Power-Supply Input. Connect a 0.1µF capacitor from VDD to VSS.

VDD

Clock Output, nominally 50kHz

CK50

Chip Current Bias Source. Connect an external 402k

Ω ±1% resistor between VDD and NBIAS.

NBIAS

Pin Description

Chip-Select Input. The MAX1459 is selected when this pin is high. When low, OUT and DIO become high

impedance. Internally pulled to VDD with a 1M

Ω (typical) resistor. Leave unconnected for normal operation.

Data Clock Input. Used only during programming/testing. Internally pulled to VSS with a 1M

Ω (typical) resistor.

Data is clocked in on the rising edge of the clock. Recommended SCLK frequency is below 50kHz.

SCLK

FUNCTION

NAME

Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.

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