Octal SMBus-to-Parallel I/O Expanders

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7

SMBus Interface Operation

The SMBus serial interface is a 2-wire interface with

multi-mastering capability. The MAX1608/MAX1609 are

2-wire slave-only devices and employ standard SMBus

write-byte, send-byte, read-byte, and receive-byte

protocols (Figure 2) as documented in “System

Management Bus Specification v1.08” (available at

www.sbs-forum.org). SMBDATA and SMBCLK are

Schmitt-triggered inputs that can accommodate slower

edges; however, the rising and falling edges should still

be faster than 1µs and 300ns, respectively.

Communication starts with the master signaling the

beginning of a transmission with a START condition,

which is a high-to-low transition on SMBDATA while

SMBCLK is high. When the master has finished com-

municating with the slave, it issues a STOP condition,

which is a low-to-high transition on SMBDATA while

SMBCLK is high (Figures 3 and 4). The bus is then free

for another transmission from any master on the bus.

The address byte, command byte, and data byte are

transmitted between the START and STOP conditions.

Figures 3 and 4 show the timing diagrams for signals

on the 2-wire interface. The SMBDATA state is allowed

to change only while SMBCLK is low, except for the

START and STOP conditions. Data is transmitted in 8-

bit words and is sampled on the rising edge of SMB-

CLK. Nine clock cycles are required to transfer each

byte in or out of the MAX1608/MAX1609 (Figure 2),

since either the master or the slave acknowledges

receipt of the correct byte during the ninth clock. The

IC responds to the address selected by the ADD0 and

ADD1 pins (Table 1).

If the MAX1608/MAX1609 receive the correct slave

address followed by RW = 0, the selected device

expects to receive one or two bytes of information. If

the device detects a START or STOP condition prior to

clocking in a full additional byte of data, it considers

this an error condition and disregards all of the data. If

no error occurs, the registers are updated immediately

after the falling edge of the acknowledge clock pulse

(Figure 5). If the MAX1608/MAX1609 receive the cor-

rect slave address followed by RW = 1, the selected

device expects to clock out the contents of the previ-

ously accessed register during the next byte transfer.

A third interface line (SMBSUS) is used to execute com-

mands asynchronously from previously stored registers

(see SMBSUS (Suspend-Mode) Input section).

SMBus Addressing

After the START condition, the master transmits a 7-bit

address followed by the RW bit (Figure 2). If the

MAX1608/MAX1609 recognizes its own address, it

sends an acknowledgment pulse by pulling SMBDATA

low.

Each slave responds to only two addresses: its own

unique address (set by ADD1 and ADD0, Table 1), and

the alert response address (0x19). The device’s unique

address is determined at power-up, with a software

sample-address-pin command (SAP), or a software

power-on-reset command (SPOR). The MAX1608/

MAX1609 address pins (ADD1–ADD0) are high imped-

ance except when ADD1–ADD0 are sampled, which

occurs during power-up and when requested (SPOR,

RAP). During sampling, the equivalent input circuit can

be described as a resistor-divider from V+ to GND

(20k

Ω each), which momentarily bias the pins to mid-

supply if they are left floating. To set the ADD_ pins

high or low, connect or drive the pins to the rails (V+ or

GND) to guarantee a correct level detection. During

sampling, the pins draw a momentary input bias cur-

rent (V+ / 20k

Ω). Also, stray capacitance in excess of

50pF on the ADD_ pins when floating may cause

address recognition problems.

SMBus Commands

The 8-bit command byte (Table 2) is the master index

that points to the registers within the MAX1608/MAX1609.

The devices include ten registers: the data registers

(NDR1–NDR3, SDR1–SDR3) are accessed through

both the read-byte and write-byte protocols (Figure 2),

the RSB and MDIF registers are accessed with the

read-byte protocols, and the RAP and SPOR registers

GND

0010 100

GND

V+

0010 110

High-Z

GND

1100 100

GND

High-Z

High-Z

1100 101

High-Z

V+

1100 110

V+

V+

0111 010

ADD1

ADDRESS (A6–A0)

ADD0

V+

High-Z

0111 001

V+

GND

0111 000

High-Z

0010 101

GND

MAX1608

MAX1609

0110 010

0100 100

0100 110

1101 100

1101 101

1101 110

0110 001

0110 000

0100 101

Table 1. Slave Addresses