±80V Fault-Protected, 2Mbps,

Low Supply Current CAN Transceiver

4

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TIMING CHARACTERISTICS

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

0.5

Ω (500kbps)

2

Ω (125kbps)

8

Minimum Bit Time

Ω (62.5kbps)

25

µs

Delay TXD to Bus Active

40

ns

Delay TXD to Bus Inactive

75

ns

120

ns

Ω (500kbps)

0.4

Ω (125kbps)

1.6

Delay TXD to Receiver Active

Ω (62.5kbps)

5.0

µs

130

ns

Ω (500kbps)

0.45

Ω (125kbps)

1.6

Delay TXD to Receiver Inactive

Ω (62.5kbps)

5.0

µs

Ω (500kbps)

14

Ω (125kbps)

7

Differential Output Slew Rate

|SR|

Ω (62.5kbps)

1.6

V/µs

Time to Wakeup: CANH > 9V

10

µs

Time to Sleep Mode when Bus Is

Recessive

10

47

ms

Note 1: As defined by ISOSHDN, bus value is one of two complementary logical values: dominant or recessive. The dominant value

represents the logical 1 and the recessive represents the logical 0. During the simultaneous transmission of the dominant

and recessive bits, the resulting bus value is dominant. For MAX3053 values, see the truth table in the Transmitter and

Receiver sections.

Note 2: The ESD structures do not short out CANH and CANL under an ESD event while -7V < CANH, CANL < +12V.