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9DB233 Datasheet(PDF) 4 Page - Integrated Circuit Systems |
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9DB233 Datasheet(HTML) 4 Page - Integrated Circuit Systems |
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4 / 17 page  9DB233 TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 IDT® TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 4 9DB233 REV E 021914 Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 9DB233. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Electrical Characteristics–Clock Input Parameters Electrical Characteristics–Current Consumption PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES 3.3V Core Supply Voltage VDDA 4.6 V 1,2 3.3V Logic Supply Voltage VDD 4.6 V 1,2 Input Low Voltage VIL GND-0.5 V 1 Input High Voltage VIH Except for SMBus interface VDD+0.5V V 1 Input High Voltage VIHSMB SMBus clock and data pins 5.5V V 1 Storage Temperature Ts -65 150 °C 1 Junction Temperature Tj 125 °C 1 Input ESD protection ESD prot Human Body Model 2000 V 1 1Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied nor guaranteed. TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Input High Voltage - DIF_IN VIHDIF Differential inputs (single-ended measurement) 600 800 1150 mV 1 Input Low Voltage - DIF_IN VILDIF Differential inputs (single-ended measurement) VSS - 300 0 300 mV 1 Input Common Mode Voltage - DIF_IN VCOM Common Mode Input Voltage 300 400 1000 mV 1 Input Amplitude - DIF_IN VSWING Peak to Peak value 300 1450 mV 1 Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 1,2 Input Leakage Current IIN VIN = VDD , VIN = GND -5 -0.02 5 uA 1 Input Duty Cycle dtin Measurement from differential wavefrom 45 50 55 % 1 Input Jitter - Cycle to Cycle JDIFIn Differential Measurement 0 125 ps 1 1 Guaranteed by design and characterization, not 100% tested in production. 2Slew rate measured through +/-75mV window centered around differential zero TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Operating Supply Current IDD3.3OP All outputs active @100MHz, CL = Full load; 70 80 mA 1 IDD3.3PD All diff pairs driven N/A mA 1 IDD3.3PDZ All differential pairs tri-stated N/A mA 1 1Guaranteed by design and characterization, not 100% tested in production. Powerdown Current |
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