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9DB233 Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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9DB233 Datasheet(HTML) 1 Page - Integrated Circuit Systems |
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1 / 17 page  DATASHEET TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 9DB233 IDT® TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 1 9DB233 REV E 021914 Description The 9DB233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the 9DB233 suitable for Express Card applications. Recommended Application 2 output PCIe Gen3 zero-delay/fanout buffer Output Features • 2 - 0.7V current mode differential HCSL output pairs Features/Benefits • OE# pins; suitable for Express Card applications • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLL's • Spread Spectrum Compatible; tracks spreading input clock for low EMI • SMBus Interface; allows control of PLL BW and Mode Key Specifications • Cycle-to-cycle jitter < 50 ps • Output-to-output skew < 50 ps • PCIe Gen3 phase jitter < 1.0ps RMS Block Diagram SPREAD COMPATIBLE PLL CONTROL LOGIC SMBDAT SMBCLK SRC_IN SRC_IN# PLL_BW IREF DIF_0 DIF_1 OE1# OE0# |
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