9DB633

Six Output Differential Buffer for PCIe Gen3

1668E—02/19/14

Six Output Differential Buffer for PCIe Gen3

1

DATASHEET

Recommended Application:

6 output PCIe Gen3 zero-delay/fanout buffer

General Description:

The 9DB633 zero-delay buffer supports PCIe Gen3

requirements, while being backwards compatible to PCIe

Gen2 and Gen1. The 9DB633 is driven by a differential SRC

output pair from an IDT 932S421 or 932SQ420 or equivalent

main clock generator. It attenuates jitter on the input clock

and has a selectable PLL bandwidth to maximize

performance in systems with or without Spread-Spectrum

clocking. An SMBus interface allows control of the PLL

bandwidth and bypass options, while 2 clock request (OE#)

pins make the 9DB633 suitable for Express Card

applications.

Key Specifications:

•

Cycle-to-cycle jitter < 50 ps

•

Output-to-output skew < 50 ps

•

PCIe Gen3 phase jitter < 1.0ps RMS

Features/Benefits:

•

OE# pins/Suitable for Express Card applications

•

PLL or bypass mode/PLL can dejitter incoming clock

•

Selectable PLL bandwidth/minimizes jitter peaking in

downstream PLL's

•

Spread Spectrum Compatible/tracks spreading input

clock for low EMI

•

SMBus Interface/unused outputs can be disabled

Output Features:

•

6 - 0.7V current mode differential HCSL output pairs

Block Diagram

SPREAD

COMPATIBLE

PLL

CONTROL

LOGIC

SMBDAT

SMBCLK

SRC_IN

SRC_IN#

PLL_BW

IREF

DIF1

DIF4

OE4#

OE1#

DIF(0,2,3,5)