REVISION 1 09/23/14

5

PORT SYNCHRONIZER FOR IEEE 1588 AND

SYNCHRONOUS ETHERNET

82P33724 SHORT FORM DATA SHEET

2

PIN DESCRIPTION

Table 1: Pin Description

Pin No.

Name

I/O

Type

Description

Global Control Signal

6OSCI

I

CMOS

OSCI: Crystal Oscillator System Clock

A clock provided by a crystal oscillator is input on this pin. It is the system clock for the

device. The oscillator frequency is selected via pins XO_FREQ0 ~ XO_FREQ2

59

SONET/SDH/

LOS3

I

pull-down

CMOS

SONET/SDH: SONET / SDH Frequency Selection

During reset, this pin determines the default value of the IN_SONET_SDH bit:

High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET);

Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH).

After reset, the value on this pin takes no effect.

LOS3- This pin is used to disqualify input clocks. See input clocks section for more details.

52

RSTB

I

pull-up

CMOS

RSTB: Reset

A low pulse of at least 50 µs on this pin resets the device.

If loading from an EEPROM, the maximum time from RSTB de-assert to have stable clocks

is 100ms. If not loading from EEPROM the maximum time from RSTB de-assert to have sta-

ble clocks is 5ms.

7

8

9

XO_FREQ0/

LOS0

XO_FREQ1/

LOS1

XO_FREQ2/

LOS2

I

pull-down

CMOS

XO_FREQ0 ~ XO_FREQ2: These pins set the oscillator frequency.

XO_FREQ[2:0] Oscillator Frequency (MHz)

000

10.000

001

12.800

010

13.000

011

19.440

100

20.000

101

24.576

110

25.000

111

30.720

LOS0 ~ LOS2 - These pins are used to disqualify input clocks. See input clocks section for

more details. After reset, this pin takes on the operation of LOS0-LOS2

Input Clock and Frame Synchronization Input Signal

31

32

IN1_POS

IN1_NEG

I

PECL/LVDS

IN1_POS / IN1_NEG: Positive / Negative Input Clock 1

A reference clock is input on this pin.This pin can also be used as a sync input, and in this

case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.

33

34

IN2_POS

IN2_NEG

I

PECL/LVDS

IN2_POS / IN2_NEG: Positive / Negative Input Clock 1

A reference clock is input on this pin.This pin can also be used as a sync input, and in this

case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.

35

36

IN3_POS

IN3_NEG

I

PECL/LVDS

IN3_POS / IN3_NEG: Positive / Negative Input Clock 3

A reference clock is input on this pin.This pin can also be used as a sync input, and in this

case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.

38

39

IN4_POS

IN4_NEG

I

PECL/LVDS

IN4_POS / IN4_NEG: Positive / Negative Input Clock 4

A reference clock is input on this pin.This pin can also be used as a sync input, and in this

case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.

37

IN5

I

pull-down

CMOS

IN5: Input Clock 5

A reference clock is input on this pin.This pin can also be used as a sync input, and in this

case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.

41

IN6

I

pull-down

CMOS

IN6: Input Clock 6

A reference clock is input on this pin.This pin can also be used as a sync input, and in this

case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.

Output Frame Synchronization Signal

43

FRSYNC

_8K_1PPS

OCMOS

FRSYNC_8K_1PPS: 8 kHz Frame Sync Output

An 8 kHz signal or a 1PPS sync signal is output on this pin.

44

MFRSYNC

_2K_1PPS

OCMOS

MFRSYNC_2K_1PPS: 2 kHz Multiframe Sync Output

A 2 kHz signal or a 1PPS sync signal is output on this pin.