82P33724 SHORT FORM DATA SHEET

PORT SYNCHRONIZER FOR IEEE 1588 AND

SYNCHRONOUS ETHERNET

6

REVISION 1 09/23/14

Output Clock

30

28

OUT1

OUT2

OCMOS

OUT1 ~ OUT2: Output Clock 1 ~ 2

25

26

OUT3_POS

OUT3_NEG

O

PECL/LVDS OUT3_POS / OUT3_NEG: Positive / Negative Output Clock 3

This output is set to LVDS by default.The LVDS output has internal 100 ohm termination.

21

22

OUT4_POS

OUT4_NEG

O

PECL/LVDS OUT4_POS / OUT4_NEG: Positive / Negative Output Clock 4

This output is set to LVDS by default.The LVDS output has internal 100 ohm termination.

71

70

OUT5_POS

OUT5_NEG

O

PECL/LVDS OUT5_POS / OUT5_NEG: Positive / Negative Output Clock 5

This output is set to LVDS by default.The LVDS output has internal 100 ohm termination.

68

67

OUT6_POS

OUT6_NEG

O

PECL/LVDS OUT6_POS / OUT6_NEG: Positive / Negative Output Clock 6

This output is set to LVDS by default.The LVDS output has internal 100 ohm termination.

65

63

OUT7

OUT8

OCMOS

OUT7 ~ OUT8: Output Clock 7 ~ 8

61

60

OUT9

OUT10

OCMOS

OUT9 ~ OUT10: Output Clock 9 ~ 10

Miscellaneous

13

VC1

O

Analog

VC1: APLL1 VC Output

An external RC filter (a resistor in series with a capacitor to ground, and another capacitor in

parallel) should be connected to this pin.

1VC2

O

Analog

VC2: APLL2 VC Output

An external RC filter (a resistor in series with a capacitor to ground, and another capacitor in

parallel) should be connected to this pin.

Lock Signal

54

DPLL3_LOCK

OCMOS

DPLL3_LOCK

This pin goes high when DPLL3 is locked

56

DPLL2_LOCK

OCMOS

DPLL2_LOCK

This pin goes high when DPLL2 is locked

55

DPLL1_LOCK

OCMOS

DPLL1_LOCK

This pin goes high when DPLL1 is locked

Microprocessor Interface

57

INT_REQ

O

Tri-state

CMOS

INT_REQ: Interrupt Request

This pin is used as an interrupt request.

46

45

MPU_MODE1/

I2CM_SCL

MPU_MODE0/

I2CM_SDA

I/O

pull-up

CMOS/

Open Drain

MPU_MODE[1:0]: Microprocessor Interface Mode Selection

During reset, these pins determine the default value of the MPU_SEL_CNFG[1:0] bits as fol-

lows:

00: I2C mode

01: SPI mode

10: UART mode

11: I2C master (EEPROM) mode

I2CM_SCL: Serial Clock Line

In I2C master mode, the serial clock is output on this pin.

I2CM_SDA: Serial Data Input for I2C Master Mode

In I2C master mode, this pin is used as the for the serial data.

Table 1: Pin Description (Continued)

Pin No.

Name

I/O

Type

Description