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82P33741 Datasheet(PDF) 3 Page - Integrated Circuit Systems |
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82P33741 Datasheet(HTML) 3 Page - Integrated Circuit Systems |
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3 / 12 page ![]() 82P33741 SHORT FORM DATA SHEET REVISION 1 09/23/14 3 PORT SYNCHRONIZER FOR IEEE 1588 AND 10G/40G SYNCHRONOUS ETHERNET I FUNCTIONAL BLOCK DIAGRAM Figure 1. Functional Block Diagram Control and Status Registers OutDiv OutDiv I2C Slave JTAG I2C Master Reference monitors Reference selection Frac-N input dividers SYS PLL DPLL2 APLL1 APLL2 OutDiv OutDiv OutDiv DPLL1 OUT3p/n OUT4p/n OUT5p/n OUT6p/n OUT7 System Clock LOS0 / XO_FREQ0 LOS1 / XO_FREQ1 LOS2 / XO_FREQ2 LOS3 ex_sync module IN3(P/N) IN4(P/N) IN5(P/N) IN1(P/N) IN2(P/N) IN6(P/N) IN7 IN8 IN9 IN10 IN11 IN12 FRSYNC_8K_1PPS MFRSYNC_2K_1PPS Crystal OutDiv OUT1 OutDiv OUT2 OutDiv OutDiv OUT10p/n OUT11p/n APLL3 (VCXO) OutDiv OutDiv OUT8 OUT9 DPLL3 |
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