82P33741 SHORT FORM DATA SHEET

REVISION 1 09/23/14

7

PORT SYNCHRONIZER FOR IEEE 1588 AND

10G/40G SYNCHRONOUS ETHERNET

Lock Signal

E9

DPLL3_LOCK

OCMOS

DPLL3_LOCK

This pin goes high when DPLL3 is locked

G9

DPLL2_LOCK

OCMOS

DPLL2_LOCK

This pin goes high when DPLL2 is locked

H9

DPLL1_LOCK

OCMOS

DPLL1_LOCK

This pin goes high when DPLL1 is locked

Microprocessor Interface

J9

INT_REQ

O

Tri-state

CMOS

INT_REQ: Interrupt Request

This pin is used as an interrupt request. The output characteristics are determined by the

HZ_EN bit (b1, 0CH) and the INT_POL bit (b0, 0CH).

B11

C11

MPU_MODE1/

I2CM_SCL

MPU_MODE0/

I2CM_SDA

I/O

pull-up

CMOS/

Open Drain

MPU_MODE[1:0]: Microprocessor Interface Mode Selection

During reset, these pins determine the default value of the MPU_SEL_CNFG[1:0] bits as fol-

lows:

00: I2C mode

01 ~ 10: Reserved

11: EEPROM mode

I2CM_SCL: Serial Clock Line

In I2C master mode, the serial clock is output on this pin.

I2CM_SDA: Serial Data Input for I2C Master Mode

In I2C master mode, this pin is used as the for the serial data.

D9

I2C_AD2

I

pull-down

CMOS

I2C_AD2: Device Address Bit 2

I2C_AD[2:0] pins are the address bus of the microprocessor interface.

E5

I2C_AD1

I

pull-down

CMOS

I2C_AD1: Device Address Bit 1

2C_AD[2:0] pins are the address bus of the microprocessor interface.

D10

I2C_SCL

I

pull-down

CMOS

I2C_SCL: Serial Clock Line

The serial clock is input on this pin.

C5

I2C_SDA

I/O

pull-up

Open Drain

I2C_SDA: Serial Data Input/Output

This pin is used as the input/output for the serial data.

JTAG (per IEEE 1149.1)

F1

TMS

I

pull-up

CMOS

TMS: JTAG Test Mode Select

The signal on this pin controls the JTAG test performance and is sampled on the rising edge

of TCK.

K3

TRSTB

I

pull-up

CMOS

TRST: JTAG Test Reset (Active Low)

A low signal on this pin resets the JTAG test port.

This pin should be connected to ground when JTAG is not used.

G1

TCK

I

pull-down

CMOS

TCK: JTAG Test Clock

The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge

of TCK and TDO is updated on the falling edge of TCK.

If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely

retain their state.

L3

TDI

I

pull-up

CMOS

TDI: JTAG Test Data Input

The test data are input on this pin. They are clocked into the device on the rising edge of

TCK.

L5

TDO

O

tri-state

CMOS

TDO: JTAG Test Data Output

The test data are output on this pin. They are clocked out of the device on the falling edge of

TCK.

TDO pin outputs a high impedance signal except during the process of data scanning.

Table 1: Pin Description (Continued)

Pin No.

Name

I/O

Type

Description