Quad, Rail-to-Rail, Fault-Protected,

SPST Analog Switches

10

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(NO) switch is shown; the normally closed (NC) config-

uration is identical except the logic-level translator

becomes an inverter. The analog switch is formed by

the parallel combination of N-channel FET N1 and P-

channel FET P1, which are driven on and off simultane-

ously according to the input fault condition and the

logic-level state.

Normal Operation

Two comparators continuously compare the voltage on

the NO_ (or NC_) pin with V+ and V-. When the signal

on NO_ or NC_ is between V+ and V- the switch acts

normally, with FETs N1 and P1 turning on and off in

response to IN_ signals. The parallel combination of

N1 and P1 forms a low-value resistor between NO_ (or

NC_) and COM_ so that signals pass equally well in

either direction.

Positive Fault Condition

When the signal on NO_ (or NC_) exceeds V+ by about

50mV, the high-fault comparator output is high, turning

off FETs N1 and P1. This makes the NO_ (or NC_) pin

high impedance regardless of the switch state. If the

switch state is “off”, all FETs are turned off and both

NO_ (or NC_) and COM_ are high impedance. If the

switch state is “on”, FET P2 is turned on, sourcing cur-

rent from V+ to COM_.

Negative Fault Condition

When the signal on NO_ (or NC_) exceeds V- by about

50mV, the low-fault comparator output is high, turning

off FETs N1 and P1. This makes the NO_ (or NC_) pin

high impedance regardless of the switch state. If the

switch state is “off,” all FETs are turned off and both

NO_ (or NC_) and COM_ are high impedance. If the

switch state is “on,” FET N2 is turned on, sinking cur-

rent from COM_ to V-.

Transient Fault Response and Recovery

When a fast rise-time and fall-time transient on IN_

exceeds V+ or V-, the output (COM_) follows the input

(IN_) to the supply rail with only a few nanoseconds

delay. This delay is due to the switch on-resistance and

circuit capacitance to ground. When the input transient

returns to within the supply rails, however, there is a

longer output recovery time delay. For positive faults, the

recovery time is typically 3.5µs. For negative faults, the

recovery time is typically 1.3µs. These values depend on

the COM_ output resistance and capacitance, and are

not production tested or guaranteed. The delays are not

dependent on the fault amplitude. Higher COM_ output

resistance and capacitance increase recovery times.

COM_ and IN_ Pins

FETs N2 and P2 can source about ±10mA from V+ or V-

to the COM_ pin in the fault condition. Ensure that if the

COM_ pin is connected to a low-resistance load, the

absolute maximum current rating of 30mA is never

exceeded, both in normal and fault conditions.

The GND, COM_, and IN_ pins do not have fault protec-

tion. Reverse ESD-protection diodes are internally con-

nected between GND, COM_, IN_ and both V+ and V-. If

a signal on GND, COM_, or IN_ exceeds V+ or V- by

more than 300mV, one of these diodes will conduct

heavily. During normal operation these reverse-biased

ESD diodes leak a few nanoamps of current to V+ and V-.

Fault-Protection Voltage and Power Off

The maximum fault voltage on the NC_ or NO_ pins is

±36V with power applied and ±40V with power off.

Failure Modes

The MAX4511/MAX4512/MAX4513 are not lightning

arrestors or surge protectors.

Exceeding the fault-protection voltage limits on NO_ or

NC_, even for very short periods, can cause the device

to fail. The failure modes may not be obvious, and fail-

ure in one switch may or may not affect other switches

in the same package.

Ground

There is no connection between the analog signal

paths and GND. The analog signal paths consist of an

N-channel and P-channel MOSFET with their sources

and drains paralleled and their gates driven out of

phase to V+ and V- by the logic-level translators.

V+ and GND power the internal logic and logic-level

translators and set the input logic thresholds. The logic-

level translators convert the logic levels to switched V+

and V- signals to drive the gates of the analog switch-

es. This drive signal is the only connection between the

power supplies and the analog signals. GND, IN_, and

COM_ have ESD-protection diodes to V+ and V-.

IN_ Logic-Level Thresholds

The logic-level thresholds are CMOS and TTL compati-

ble when V+ is +15V. As V+ is raised the threshold

increases slightly, and when V+ reaches 25V the level

threshold is about 2.8V—above the TTL output high

level minimum of 2.4V, but still compatible with CMOS

outputs (see

Typical Operating Characteristics).

Increasing V- has no effect on the logic-level thresholds,

but it does increase the gate-drive voltage to the signal

FETs, reducing their on-resistance.