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TIMING CHARACTERISTICS (Note 12)

(VCC = +5V, VEE = -5V, -2V ≤ VIN ≤ +2V, output load resistor (RL) = 150Ω, TA = TMIN to TMAX, unless otherwise noted.)

CONDITIONS

200

tDO

SCLK Fall to DOUT

tDH

DIN to SCLK Rise Hold Time

tDS

DIN to SCLK Rise Setup Time

tCL

SCLK Pulse Width Low

tCH

SCLK Pulse Width High

tCSS

–

—

–

Fall to SCLK Rise

tCSO

SCLK to

–

—

–

Fall

tUPS

–

—

–

Rise to

–

—

–

Fall Setup Time

tCES

–

—

–

Fall to

–

—

–

Fall Setup Time

tADH

Address to

–

—

–

Rise Hold Time

tUP

–

—

–

Pulse Width Low

tWRS

–

—

–

Rise to

–

—

–

Fall Setup Time

tDH

Data to

–

—

–

Rise Hold Time

tDS

Data to

–

—

–

Rise Setup Time

tCEH

–

—

–

Rise to

–

—

–

Rise Hold Time

tWR

–

—

–

Pulse Width Low

UNITS

MIN

MAX

SYMBOL

PARAMETER

tADS

Address to

–

—

–

Fall Setup Time

tCSH

SCLK Rise to

–

—

–

Rise

tCS1

–

—

–

Rise to SCLK Rise

100

tCSW

–

—

–

Pulse Width High

PARALLEL-MODE TIMING (see Figure 1)

SERIAL-MODE TIMING (see Figure 6)

Note 12: Timing Characteristics are guaranteed by design.

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