Low-Voltage, Combination Single-Ended

8-to-1/Differential 4-to-1 Multiplexer

______________________________________________________________________________________

11

Test Circuits/Timing Diagrams

(continued)

GND

LATCH,

EN

+5V

-5V

V+

NLATCH

A3

V-

A2

A1

NO8

MAX4598

A0

CHANNEL

SELECT

NO1

COM_

1MHz

CAPACITANCE

ANALYZER

Figure 6. NO_/COM_ Capacitance

LATCH

ADDRESS

NOTE: TIMING MEASUREMENT REFERENCE LEVEL IS

2

50%

+5V

-5V

GND

V+

V-

A1

A2

A3

EN

+3V

COM

LATCH

A0

MAX4598

NO2

NO1, NO3–NO8

NLATCH

Figure 7. Setup Time, Hold Time

TRANSISTOR COUNT: 287

SUBSTRATE CONNECTED TO V+

____________________Chip Topography

NO8

NO6

NO7

NO5

A0

A1

COMB GND

A2

A3

0.104"

(2.64mm)

0.092"

(2.34mm)

V- V+

NO4

NO2

NO1

NO3

COMA

LATCH

EN

NLATCH