3V/5V, 4

Ω, Wideband Quad

2:1 Analog Multiplexer

6

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Detailed Description

age, quad 2:1 analog multiplexer/demultiplexer that

operates from a +1.8V to +5.5V single supply. The

ous currents to be switched in a variety of applications.

Digital Interface

A0 and EN are CMOS digital inputs that meet TTL logic

levels when V+ = 5V. Note that A0 and EN can exceed

the voltage at V+ to a maximum of +5.5V. This feature

allows operation of the MAX4674 from a +3.3V supply

while controlling it with 5V CMOS logic signals.

The Pin Configuration/Functional Diagram/Truth Table

located on the first page of this data sheet details the

operation of the MAX4674.

Applications Information

Power-Supply Considerations

Overview

The MAX4674 construction is typical of most CMOS

analog switches. It has two supply pins, V+ and GND,

used to drive the internal CMOS switches and set the

limits of the analog voltage on any switches. Reverse

ESD-protection diodes are internally connected

between each analog-signal pin and both V+ and

GND. If any analog signal exceeds V+ and GND, one

of these diodes conducts. During normal operation,

these and other reverse-biased ESD diodes leak, form-

Virtually all the analog leakage current comes from the

ESD diodes. Although the ESD diodes on a given sig-

nal pin are identical and therefore fairly well balanced,

they are reverse biased differently. Each is biased by

either V+ or GND and the analog signal. This means

their leakages will vary as the signal varies. The differ-

ence in the two-diode leakages to the V+ and GND

pins constitutes the analog-signal-path leakage current.

All analog leakage current flows between each pin and

one of the supply terminals, not to the other switch ter-

minal, which is why both sides of a given switch can

show leakage currents of either the same or opposite

polarity.

V+ and GND power the internal logic and set the input

logic limits. Logic inputs have ESD-protection diodes to

ground.

The logic-level thresholds are TTL/CMOS compatible

when V+ is +5V. As V+ rises, the threshold increases;

as V+ falls, the threshold decreases. For example,

Pin Description

PIN

QSOP/TSSOP/SO

20 QFN

16 QFN

NAME

FUNCTION

1

20

15

A0

Address Input

2

1

16

NC1

Normally Closed Terminal

3

2

1

NO1

Normally Open Terminal

4

3

2

COM1

Analog Switch Common Terminal

5

4

3

NC2

Normally Closed Terminal

6

5

4

NO2

Normally Open Terminal

7

6

5

COM2

Analog Switch Common Terminal

—

7, 9, 17, 19

—

N.C.

No Connection

8

8

6

GND

Ground

9

10

7

COM3

Analog Switch Common Terminal

10

11

8

NO3

Normally Open Terminal

11

12

9

NC3

Normally Closed Terminal

12

13

10

COM4

Analog Switch Common Terminal

13

14

11

NO4

Normally Open Terminal

14

15

12

NC4

Normally Closed Terminal

15

16

13

EN

Output Enable, Active Low

16

18

14

V+

Positive Supply Voltage