ICS83948I

LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER

IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR

2

ICS83948AYI REV. C NOVEMBER 14, 2012

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Function Tables

Table 3A. Clock Select Function Table

Number

Name

Type

Description

1

CLK_SEL

Input

Pullup

Clock select input. When HIGH, selects LVCMOS_CLK input.

When LOW, selects CLK/nCLK inputs. LVCMOS / LVTTL interface levels.

2

LVCMOS_CLK

Input

Pullup

Single-ended clock input. LVCMOS/LVTTL interface levels.

3

CLK

Input

Pullup

Non-inverting differential clock input.

4

nCLK

Input

Pulldown

Inverting differential clock input.

5

CLK_EN

Input

Pullup

Clock enable pin. LVCMOS/LVTTL interface levels.

6

OE

Input

Pullup

Output enable pin. LVCMOS/LVTTL interface levels.

Power

Positive supply pin.

8, 12, 16,

20, 24, 28, 32

GND

Power

Power supply ground.

9, 11, 13,

15, 17, 19,

21, 23, 25,

27, 29, 31

Q11, Q10, Q9,

Q8, Q7, Q6,

Q5, Q4, Q3,

Q2, Q1, Q0

Output

Single-ended clock outputs. LVCMOS/LVTTL interface levels.

10, 14, 18,

22, 26, 30

Power

Output supply pins.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

4

pF

Input Pullup Resistor

51

k



51

k



Power Dissipation Capacitance

(per output)

25

pF

Output Impedance

7



Control Input

Clock

CLK_SEL

CLK/nCLK

LVCMOS_CLK

0

Selected

De-selected

1

De-selected

Selected