Calibrated, Quad, 12-Bit

Voltage-Output DACs with Serial Interface

The input impedance at each reference input is code

dependent, ranging from a low value of typically 6k

Ω

(with an input code of 0101 0101 0101) to a high value

of 60k

Ω (with an input code of 0000 0000 0000). Since

the input impedance at the reference pins is code

dependent, load regulation of the reference source is

important.

The REFAB and REFCD reference inputs have a 5k

Ω

guaranteed minimum input impedance. When the two

reference inputs are driven from the same source, the

effective minimum impedance becomes 2.5k

Ω. A volt-

age reference with a load regulation of 0.001%/mA,

such as the MAX674, would typically deviate by

0.164LSB (0.328LSB worst case) when simultaneously

driving both MAX536 reference inputs at 10V.

An op amp, such as the MAX400 or OP07, can be used

to buffer the reference to increase reference accuracy.

The op amp’s closed-loop output impedance should be

kept below 0.05

Ω to ensure an error of less than

0.08LSB. Reference accuracy is also improved by driv-

ing the REFAB and REFCD pins separately, or by using

a reference with excellent accuracy and superior load

regulation, such as the MAX676/MAX677/MAX678.

The reference input capacitance is also code depen-

dent and typically ranges from 125pF to 300pF.

Output Buffer Amplifiers

All MAX536/MAX537 voltage outputs are internally

buffered by precision unity-gain followers with a typical

slew rate of 5V/

µs for the MAX536 and 3V/µs for the

MAX537.

With a full-scale transition at the MAX536 output (0V to

10V or 10V to 0V), the typical settling time to ±1/2LSB is

3

µs when loaded with 5kΩ in parallel with 100pF (loads

less than 5k

Ω degrade performance).

With a full-scale transition at the MAX537 output (0V to

2.5V or 2.5V to 0V), the typical settling time to ±1/2LSB

is 5

µs when loaded with 5kΩ in parallel with 100pF

(loads less than 5k

Ω degrade performance).

Output dynamic responses and settling performances

of the MAX536/MAX537 output amplifier are shown in

the

Typical Operating Characteristics.

Serial-Interface Configurations

The MAX536/MAX537’s 3-wire or 4-wire serial interface is

compatible with both Microwire (Figure 2) and SPI/QSPI

high or low for a 3-wire interface, or used as the fourth

input with a 4-wire interface. The connection between

SDO and the serial-interface port is not necessary, but

may be used for data echo. (Data held in the shift register

SCK

SDI

SDO*

CS

LDAC**

SK

SO

SI*

I/O

I/O

MAX536

MAX537

MICROWIRE

PORT

5V

1k

*THE SDO-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX536,

BUT MAY BE USED FOR READBACK PURPOSES.

**THE LDAC CONNECTION IS NOT REQUIRED WHEN USING THE 3-WIRE INTERFACE.

Figure 2. Connections for Microwire

Figure 3. Connections for SPI/QSPI

SDO*

SDI

SCK

CS

LDAC**

MISO*

MOSI

SCK

I/O

I/O

SPI/QSPI

PORT

SS

5V

CPOL = 0, CPHA = 0

1k

*THE SDO-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX536,

BUT MAY BE USED FOR READBACK PURPOSES.

**THE LDAC CONNECTION IS NOT REQUIRED WHEN USING THE 3-WIRE INTERFACE.

MAX536

MAX537

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