S1167 datasheet(13/31 Pages) SII

13 / 31 page

ULTRA LOW CURRENT CONSUMPTION, HIGH RIPPLE REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR

Rev.3.2_00

S-1167 Series

Seiko Instruments Inc.



Operation

1. Basic Operation

Figure 12 shows the block diagram of the S-1167 Series.

The error amplifier compares the reference voltage (Vref) with feedback voltage (Vfb), which is the output voltage

resistance-divided by feedback resistors (Rs and Rf). It supplies the gate voltage necessary to maintain the constant

output voltage which is not influenced by the input voltage and temperature change, to the output transistor.

*1. Parasitic diode

VSS

Current

supply

−

Vfb

Vref

VIN

VOUT

Error

amplifier

Reference voltage

circuit

Figure 12

2. Output Transistor

In the S-1167 Series, a low on-resistance P-channel MOS FET is used as the output transistor.

Be sure that VOUT does not exceed VIN

+ 0.3 V to prevent the voltage regulator from being damaged due to reverse

current flowing from the VOUT pin through a parasitic diode to the VIN pin, when the potential of VOUT became higher

than VIN.

S1167 Datasheet(PDF) 13 Page - Seiko Instruments Inc