MAX555 datasheet(3/12 Pages) MAXIM

3 / 12 page

300Msps, 12-Bit DAC with

Complementary Voltage Outputs

_______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AVEE = DVEE = -5.2V, VREF = 1.000V, TMIN to TMAX = 0°C to +70°C, unless otherwise noted.) (Note 2.)

AVEE = DVEE = -5.2V

VIL = -1.95V

VOUT, VOUT

VIH = -0.75V

VREF = 1.000V, RL = 0Ω

TA = +25°C

Bypass = 1, transparent mode (Notes 4, 7)

-3dB

VREF = 1.000V

Bypass = 0, clocked mode (Notes 4, 7)

Bypass = 1, transparent mode (Notes 4, 7)

CONDITIONS

110

150

190

DIEE

Digital Power-Supply Current

AIEE

Analog Power-Supply Current

COUT

Output Capacitance

Ω

49.5

50.0

50.5

ROUT

Output Resistance

19.0

20.0

21.0

IOUT

Full-Scale Output Current

µV

-250

250

VOS

Input Offset Voltage

kV/V

320

AVOL

Open-Loop Gain

MHz

Multiplying Input Bandwidth

Ω

775

800

825

RIN

Amplifier Input Resistance

600

tDD

MSBs Decode Delay

µA

IIL

Input Current, Logic Low

µA

200

IIH

Input Current, Logic High

2.1

tPD1

MSBs Data-to-VOUT

Propagation Delay

1.5

tPD2

LSBs Data-to-VOUT

Propagation Delay

2.0

tPD3

Clock-to-VOUT

Propagation Delay

1.8

tHOLD

Data-to-Clock Hold Time

-1.1

-0.75

VIH

Logic "1" Voltage

-2.0

-1.95

-1.48

VIL

Logic "0" Voltage

tSU

Data-to-Clock Setup Time

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

0.98

1.3

Power Dissipation

°C/W

TJA

Package Thermal Resistance,

Junction to Ambient

Note 2: All devices are 100% production tested at +25°C and are guaranteed by design for TA = TMIN to TMAX as specified.

Note 3: The gain-error method of calculation is shown below:

Definition:

[VMEASURE(FS) - VIDEAL(FS)] x 100

EG(%) = ––––––––––––––––––––––––––––––––––

VIDEAL(FS)

where FS indicates full-scale measurements.

EG Method:

EG = [(4096 / 4095) VMEASURE - 16(VREF / RIN) (ROUT)] x 100

–––––––––––––––––––––––––––––––––––––––––––––––––– %

16(VREF / RIN) (ROUT)

= [(4096 / 4095) VMEASURE - 1] x 100

––––––––––––––––––––––––––––––––- %

where: VREF = 1.000V, RIN = 800Ω, ROUT = 50Ω, VMEASURE = VOUT (FS).

Note 4: Dynamic and timing specifications are obtained from device characterization and simulation testing and are not production tested.

Note 5: Spurious-free dynamic range is measured from the fundamental frequency to any harmonic or non-harmonic spurs within

the bandwidth fCLK/2, unless otherwise specified.

Note 6: Guaranteed by design.

Note 7: Timing definitions are detailed in Figure 2.

Minimum data rate = DC (Note 6)

MHz

300

Data Update Rate

DIGITAL INPUTS

CONTROL AMPLIFIER

OUTPUT PERFORMANCE

POWER SUPPLIES

DIGITAL TIMING

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