Low-Power, SC70/SOT µP Reset Circuits with

Capacitor-Adjustable Reset Timeout Delay

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5

The reset delay time is set by a current/capacitor-con-

trolled ramp compared to an internal 0.65V reference.

An internal 240nA ramp current source charges the

external capacitor. The charge to the capacitor is

cleared when a reset condition is detected. Once the

reset condition is removed, the voltage on the capacitor

capacitor must ramp to 0.65V to deassert the reset.

ceramic is recommended.

Operating as a Voltage Detector

The MAX6340/MAX6421–MAX6426 can be operated in a

voltage detector mode by floating the SRT pin. The reset

threshold are not significantly different. The reset output is

deasserted smoothly without false pulses.

Applications Information

Interfacing to Other Voltages for Logic

Compatibility

The open-drain outputs of the MAX6340/MAX6423/

MAX6425/MAX6426 can be used to interface to µPs with

other logic levels. As shown in Figure 1, the open-drain

output can be connected to voltages from 0 to 5.5V. This

allows for easy logic compatibility to various µPs.

Wired-OR Reset

To allow auxiliary circuitry to hold the system in reset,

an external open-drain logic signal can be connected

to the open-drain RESET of the MAX6340/MAX6423/

MAX6425/MAX6426, as shown in Figure 2. This config-

uration can reset the µP, but does not provide the reset

timeout when the external logic signal is released.

In addition to issuing a reset to the µP during power-up,

power-down, and brownout conditions, these supervisors

are relatively immune to short-duration negative-going

transients (glitches). The graph Maximum Transient

Duration vs. Reset Threshold Overdrive in the Typical

Operating Characteristics shows this relationship.

The area below the curve of the graph is the region in

which these devices typically do not generate a reset

pulse. This graph was generated using a negative-

tude indicated (reset-threshold overdrive). As the mag-

nitude of the transient decreases (farther below the

reset threshold), the maximum allowable pulse width

below the reset threshold and lasts 50µs or less does

not cause a reset pulse to be issued.

Ensuring a Valid RESET or RESET

ing (sourcing) capabilities decline drastically. In the

case of the MAX6421/MAX6424, high-impedance

CMOS-logic inputs connected to RESET can drift to

undetermined voltages. This presents no problems in

most applications, since most µPs and other circuitry

In those applications where RESET must be valid down

to zero, adding a pulldown resistor between RESET

and ground sinks any stray leakage currents, holding

RESET low (Figure 3). The value of the pulldown resis-

tor is not critical; 100k

Ω is large enough not to load

RESET and small enough to pull RESET to ground. For

applications using the MAX6422, a 100k

Ω pullup resis-

MAX6340

MAX6423

MAX6425

MAX6426

RESET

N

N

GND

OPEN-DRAIN

LOGIC

µP

RESET

10k

Ω

Figure 2. Wired-OR Reset Circuit