5-Pin µP Supervisory Circuits with

Watchdog and Manual Reset

______________________________________________________________________________________

11

Figure 10 shows an example of a flow diagram where

the I/O driving the watchdog input is set high at the

beginning of the program, set low at the end of every

subroutine or loop, then set high again when the pro-

gram returns to the beginning. If the program should

hang in any subroutine, the problem would be quickly

corrected, since the I/O is continually set low and the

watchdog timer is allowed to time out, causing a reset

or interrupt to be issued. As described in the

Watchdog

Input Current section, this scheme results in higher time

average WDI current than does leaving WDI low for the

majority of the timeout period and periodically pulsing it

low-high-low.

START

SET WDI

HIGH

PROGRAM

CODE

SUBROUTINE OR

PROGRAM LOOP

SET WDI LOW

RETURN

POSSIBLE

INFINITE LOOP PATH

Figure 10. Watchdog Flow Diagram

GND

WDI

MR

RESET

MAX6316

MAX6320

SOT23-5

TOP VIEW

2

34

GND

WDI

MR

RESET

MAX6317

SOT23-5

2

34

GND

WDI

RESET

RESET

MAX6318

MAX6321

SOT23-5

2

34

GND

MR

RESET

RESET

MAX6319

MAX6322

SOT23-5

2

34

__________________Pin Configurations

MAX6316

GND

MANUAL

RESET

I/O

WDI

MR

GND

µP

RESET

RESET

Typical Operating Circuit