MAX782CSLASHD datasheet(20/32 Pages) MAXIM

20 / 32 page

Triple-Output Power-Supply

Controller for Notebook Computers

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where CRSS is the reverse transfer capacitance of the

high-side MOSFET (a data sheet parameter), f is the

switching frequency, and IDRIVE is the peak current

available from the MAX782’s large high-side gate dri-

ver outputs (DH5 or DH3, approximately 1A).

Additional switching losses are introduced by other

sources of stray capacitance at the switching node,

including the catch diode capacitance, coil interwind-

ing capacitance, and low-side switch-drain capaci-

tance. They are given as PDSW = VIN2 x CSTRAY x f,

but are usually negligible compared to CRSS losses.

The low-side switch introduces only tiny switching

losses, since its drain-source voltage is already low

when it turns on.

PDCAP = capacitor ESR loss = IRMS2 x ESR

and,

IRMS = RMS AC input current

√ VOUT(VIN - VOUT)

= ILOAD x ————————

VIN

where ESR is the equivalent series resistance of the

input bypass capacitor. Note that losses in the output

filter capacitors are small when the circuit is heavily

loaded, because the current into the capacitor is not

chopped. The output capacitor sees only the small AC

sawtooth ripple current. Ensure that the input bypass

capacitor has a ripple current rating that exceeds the

value of IRMS.

PDIC is the IC’s quiescent power dissipation and is a data

sheet parameter (6mW typically for the entire IC at VIN =

15V). This power dissipation is almost completely inde-

pendent of supply voltage whenever the +5V step-down

switch-mode power supply is on, since power to the chip

is bootstrapped from the +5V output. When calculating

the efficiency of each individual buck controller, use 3mW

for PDIC, since each controller consumes approximately

half of the total quiescent supply current.

Example: +5V buck SMPS at 300kHz, VIN = 15V, ILOAD

= 2A, RCS = RCOIL = ESR = 25mΩ, both transistors are

Si9410DY with rDS(ON) = 0.05Ω, CRSS = 160pF, and qG

= 30nC.

PDTOTAL = 400mW (I2R) + 90mW (GATE) + 36mW

(DIODE) + 22mW (TRAN) + 22mW (CAP) + 3mW (IC)

= 573mW

Efficiency = 10W/(10W + 573mW) x 100% = 94.6%

(actual measured value = 94%).

Light-Load Efficiency

Under light loads, the PWMs operate in the discontinu-

ous-conduction mode, where the inductor current dis-

charges to zero at some point during each switching

cycle. New loss mechanisms, insignificant at heavy

loads, start to become important. The basic difference

is that, in discontinuous mode, the inductor current’s

AC component is large compared to the load current.

This increases core losses and losses in the output fil-

ter capacitors. Ferrite cores are recommended over

powdered toroid types for best light-load efficiency.

At light loads, the inductor delivers triangular current

pulses rather than the nearly constant current found in

continuous mode. These pulses ramp up to a point set

by the idle-mode current comparator, which is internally

fixed at approximately 25% of the full-scale current-limit

level. This 25% threshold provides an optimum bal-

ance between low-current efficiency and output voltage

noise (the efficiency curve would actually look better if

this threshold were set at about 45%, but the output

noise would then be too high).

Reducing I2R losses though the brute-force method of

specifying huge, low-rDS(ON) MOSFETs can result in

atrocious efficiency, especially at mid-range and light-

load conditions. Even at heavy loads, the gate charge

losses introduced by huge 50A MOSFETs usually more

than offset any gain obtained through lower rDS(ON).

Layout and Grounding

Good layout is necessary to achieve the designed out-

put power, high efficiency, and low noise. Good layout

includes use of a ground plane, appropriate compo-

nent placement, and correct routing of traces using

appropriate trace widths. The following points are in

order of importance:

1. A ground plane is essential for optimum performance.

In most applications, the power supply is located on a

multilayer motherboard, and full use of the four or

more copper layers is recommended. Use the top

and bottom layers for interconnections, and the inner

layers for an uninterrupted ground plane.

2. Keep the Kelvin-connected current-sense traces

short, close together, and away from switching

nodes. See Figure 5.

3. Place the LX node components N1, N3, D3, and L1

as close together as possible. This reduces resistive

and switching losses and keeps noise due to

ground inductance confined. Do the same with the

other LX node components N2, N4, D4, and L2.

4. The input filter capacitor C1 should be less than

10mm away from N1’s drain. The connecting cop-

per trace carries large currents and must be at least

2mm wide, preferably 5mm.

Similarly, place C13 close to N2’s drain, and con-

nect them with a wide trace.

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