MAX9360ESA datasheet(6/9 Pages) MAXIM

6 / 9 page

LVTTL/TTL/CMOS-to-Differential LVECL/

ECL Translators

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Pin Description

SOT23

NAME

FUNCTION

VEE

Negative Supply Voltage. Bypass VEE to GND with 0.1µF and 0.01µF ceramic capacitors.

Place the capacitors as close to the device as possible with the smaller value capacitor

closest to the device.

LVTTL/CMOS Input for MAX9360. TTL/CMOS input for MAX9361.

3, 4

N.C.

No Connect. Connect to GND.

GND

Ground

Inverting Differential LVECL/ECL Output. Typically terminate with 50

Ω resistor to -2V.

Noninverting Differential LVECL/ECL Output. Typically terminate with 50

Ω resistor to -2V.

VCC

Positive Supply Voltage. Bypass VCC to GND with 0.1µF and 0.01µF ceramic capacitors.

Place the capacitors as close to the device as possible with the smaller value capacitor

closest to the device.

50%

tPLH

tPHL

VOH - VOL

80%

20%

80%

0 (DIFFERENTIAL)

DIFFERENTIAL WAVEFORM

SINGLE-ENDED WAVEFORMS

Q - Q

VOH

VOL

VIL

VIH

Figure 1. Input-to-Output Propagation Delay and Transition Timing Diagram

MAX9360ESA Datasheet(PDF) 6 Page - Maxim Integrated Products