MIC59P50 datasheet(2/5 Pages) MICREL

2 / 5 page

October 1998

7-59

MIC59P50

Micrel

Pin Description

Name

Description

FLAG

Error Flag. Open Collector Output is Low upon Overcurrent Fault or

Overtemperature Fault. OUTPUT ENABLE/RESET must be pulled high to

reset the flag and fault condition.

CLEAR

Sets All Latches OFF (open).

STROBE

Input Strobe Pin. Loads output latches when High.

4–11

INPUT

Parallel Inputs, 1 through 8

Output Ground (Substrate). Most negative voltage in the system connects

here.

COMMON

Transient suppression diodes cathode common pin.

14–21

OUTPUT

Parallel Outputs, 8 through 1.

Logic Positive Supply voltage.

OUTPUT ENABLE RESET

Output Enable Reset. When Low, Outputs are active. When High, outputs

are inactive and the Flag and outputs are reset from a fault condition. An

undervoltage condition emulates a high OE input.

Logic reference (Ground) pin.

Absolute Maximum Ratings T

A = +25°C

Output Voltage (V

CE) .................................................... 80V

Supply Voltage (V

DD) .................................................... 15V

DD – VEE) ............................................................... 25V

Input Voltage (V

IN) ............................... –0.3V to VDD+0.3V

Continuous Collector Current (I

C) ............................ 500mA

Protected Current ............................................ 1.5A, Note 1

Power Dissipation (P

Plastic DIP (N) ......................................................... 2.4W

Derate above T

A = +25°C ............................ 24mW/°C

PLCC (V) ................................................................. 1.6W

Derate above T

A = +25°C ............................ 16mW/°C

Wide SOIC (WM) .................................................... 1.4W

Derate above T

A = +25°C ............................ 14mW/°C

Operating Temperature (T

Plastic DIP (N), PLCC (V), SOIC (WM) .. –40

°C to +85°C

Storage Temperature (T

S) ....................... –65°C to +150°C

Junction Temperature (T

J) ...................................... +150°C

ESD ......................................................................... Note 2

Note 1:

Each channel. VEE connection must be designed to minimize

inductance and resistance.

Note 2:

Devices are input-static protected but can be damage by

extremely high static charges.

Typical Input

102030405060708090100

450

400

350

300

250

200

150

100

PERCENT DUTY CYCLE

1 or 2

NUMBER OF OUTPUTS

CONDUCTING

SIMULTANEOUSLY

MIC59P50BN

Allowable Output Current

PLCC Pin Configuration

OUT 1

OUT 2

OUT 3

OUT 4

OUT 5

OUT 6

OUT 7

IN 7

IN 6

IN 5

IN 4

IN 3

IN 2

IN 1

MIC59P50BV

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