TAS5010

SLAS328 − SEPTEMBER 2001

11

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functional description (continued)

MSB left-justified serial interface format (for 16 bits)

MSB

LSB

MSB

LSB

SCLK

LRCLK = fs

SDIN

Left Channel

Right Channel

Figure 9. MSB Left-Justified Serial Interface Format

Note the following characteristics of this protocol:

−

Left channel is received when LRCLK is high.

−

Right channel is received when LRCLK is low.

−

SDIN is sampled at the rising edge of SCLK.

DSP compatible serial interface format (for 16 bits)

SCLK

LRCLK = fs

SDIN

Left Channel

(MSB = 15)

Right Channel

(MSB = 15)

15

14

13

0

15

14

13

0

Figure 10. DSP Compatible Serial Interface Format

Note the following characteristics of this protocol:

−

Serial data is sampled with the falling edge of SCLK.

PWM Outputs

Designed to be used with the TAS5100 family of H-Bridges, the PWM outputs provide differential 3.3 V

square-wave signals. During normal operation these outputs represent the input PCM audio in the pulse-width

modulation scheme. In the hard-mute state the P outputs (PWM_AP_L and PWM_AP_R) are held low and the

M outputs (PWM_AM_L and PWM_AM_R) are held high. In the quiet-mute state the differential PWM outputs

have a 50% duty cycle.